wiring/src/w203.py
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from sheet import Sheet, STYLE, LWimport model def usbc(s, c, ref, title, sub, cable): """USB-C receptacle block at column x=c; returns dict of port y.""" Y = dict(vbus=146, cc=191, d=236, ss1=281, ss2=314, sbu=350, sh=386) s.block(ref, c, 110, 190, 300, title, sub, [("R", Y["vbus"]-110, "vbus", "VBUS A4 A9 B4 B9"), ("R", Y["cc"]-110, "cc", "CC1 / CC2 A5 / B5"), ("R", Y["d"]-110, "d", "D+ / D− A6 A7 / B6 B7"), ("R", Y["ss1"]-110, "ss1", "TX1± RX1± A2 A3 B10 B11"), ("R", Y["ss2"]-110, "ss2", "TX2± RX2± B2 B3 A10 A11"), ("R", Y["sbu"]-110, "sbu", "SBU1 / SBU2 A8 / B8"), ("R", Y["sh"]-110, "sh", "Shell · GND A1 A12 B1 B12")], title_fs=10, port_fs=7) s.label(c+95, 425, cable, 7, "middle", "#1f4e9c") # shell → chassis s.wire("BOND", [(c+190, Y["sh"]), (c+235, Y["sh"])]); s.gnd(c+235, Y["sh"], chassis=True) s.label(c+252, Y["sh"]+4, "bracket → chassis · W-19", 6.8, fill="#4c7c1c") return Y def draw(): s = Sheet("203", model.SHEETS[7][1]) s.heading(60, 66, "EXTERNAL PORTS AND M.2 MODULE CONNECTOR WIRING — Ports A / B / C (USB-C), RJ45, M.2 Key-E (Wi-Fi), M.2 M-key (NVMe)", 14) s.label(60, 81, "Logical connector wiring, NTS. USB-C pin names per the USB Type-C specification (signal groups, both orientations wired); M.2 shown as signal groups only. Pro-only population dashed. Sources: docs/00 §3.3–3.4; docs/02 §4.5; docs/05 §7; docs/08 §7; docs/09 §3.4–3.5, §5.3, §6, §9.1, §11, §13.", 8.5, fill="#333") # ================= Port A ================= c = 60; Y = usbc(s, c, "J4", "J4 — Port A USB-C 'PD / PHONE'", ["IP67 mid-mount, USB 3.2 Gen1 + PD"], "cable W-13 → iPhone / Mac / PC / PD charger") s.block("PDA", c+290, 126, 180, 84, "TPS25750-A — PD sink/source", ["VBUS → priority mux / charger · P-01", "PD sink ≤ 100 W (limit 3.3 A at 20 V);", "5 V/1.5 A source via eFuse (PR_Swap)"], [("L", Y["vbus"]-126, "vbus", None), ("L", Y["cc"]-126, "cc", None)], title_fs=9.5) s.wire("POWER", [(c+190,Y["vbus"]),(c+290,Y["vbus"])], "TVS 24 V + OVP 22 V", dy=-4, fs=6.8, arrow="both") s.wire("CTRL", [(c+190,Y["cc"]),(c+290,Y["cc"])], "TPD1E10B06 class", dy=-4, fs=6.8, arrow="both") s.block("OTG1", c+290, 224, 180, 106, "RK3588 USB3 OTG1 (SoM)", ["dwc3 peripheral, 5 Gb/s UFP gadget:", "UAS/BOT LUNs (RO default) + CDC-NCM"], [("L", Y["d"]-224, "d", None), ("L", Y["ss1"]-224, "ss1", None), ("L", Y["ss2"]-224, "ss2", None)], title_fs=9.5) s.wire("HS", [(c+190,Y["d"]),(c+290,Y["d"])], "USB 2.0 · TPD2E001", dy=-4, fs=6.8, arrow="both") s.wire("HS", [(c+190,Y["ss1"]),(c+290,Y["ss1"])], "90 Ω · TVS ≤ 0.3 pF", dy=-4, fs=6.8, arrow="both") s.wire("HS", [(c+190,Y["ss2"]),(c+290,Y["ss2"])], "SS orientation: TBD — OI-13", dy=9, fs=6.8, arrow="both", lfill="#9c1f1f") s.label(c+198, Y["sbu"]+3, "unused (N.C., TVS optional)", 6.8, fill="#777") # ================= Port B ================= c = 560; Y = usbc(s, c, "J5", "J5 — Port B USB-C 'SSD / TETHER'", ["IP67 mid-mount, USB 3.2 Gen2 host"], "cable W-14 → external SSD / tethered phone / USB cellular adapter") s.block("EFB", c+290, 118, 180, 56, "eFuse TPS2596 — Port B VBUS", ["from 5.0 V PORT B buck · P-14 · 3.3 A trip"], [("L", Y["vbus"]-118, "vbus", None)], title_fs=9.5) s.wire("POWER", [(c+290,Y["vbus"]),(c+190,Y["vbus"])], "5 V · 0.5 / 1.5 / 3 A", dy=-4, fs=6.8, arrow="end") s.block("PDB", c+290, 175, 180, 44, "TPS25750-B — Rp source ctrl", ["0.5 / 1.5 / 3 A; 3 A only with PD present"], [("L", Y["cc"]-175, "cc", None)], title_fs=9.5) s.wire("CTRL", [(c+190,Y["cc"]),(c+290,Y["cc"])], "Rp set by EC (D13)", dy=-4, fs=6.8, arrow="both") s.block("XHCI", c+290, 224, 180, 106, "ASM3142 xHCI (USB 3.2 Gen2)", ["10 Gb/s host, Gen3 ×2 on the ASM2812;", "SSD ingest or USB network-class tether"], [("L", Y["d"]-224, "d", None), ("L", Y["ss1"]-224, "ss1", None), ("L", Y["ss2"]-224, "ss2", None)], title_fs=9.5) s.wire("HS", [(c+190,Y["d"]),(c+290,Y["d"])], "USB 2.0 · TPD2E001", dy=-4, fs=6.8, arrow="both") s.wire("HS", [(c+190,Y["ss1"]),(c+290,Y["ss1"])], "90 Ω L9 ≤ 90 mm · TVS ≤ 0.3 pF", dy=-4, fs=6.8, arrow="both") s.wire("HS", [(c+190,Y["ss2"]),(c+290,Y["ss2"])], "SS orientation: TBD — OI-13", dy=9, fs=6.8, arrow="both", lfill="#9c1f1f") s.label(c+198, Y["sbu"]+3, "unused", 6.8, fill="#777") # ================= Port C ================= c = 1060; Y = usbc(s, c, "J6", "J6 — Port C USB-C 'USB4 FAST'", ["IP67 mid-mount, USB4-rated receptacle"], "cable W-15 → USB4 host / PD source (Pro); blanked TPU plug on Base") s.block("VMUX", c+290, 118, 180, 56, "TPS2121-class VBUS mux (Pro)", ["input B → BQ25792 · P-02 · Port A wins"], [("L", Y["vbus"]-118, "vbus", None)], title_fs=9.5, dashed=True) s.wire("POWER", [(c+190,Y["vbus"]),(c+290,Y["vbus"])], "Base: detect divider + TVS", dy=-4, fs=6.8, arrow="end") s.block("PDC", c+290, 180, 180, 34, "TPS25750-C — PD sink (Pro)", None, [("L", Y["cc"]-180, "cc", None)], title_fs=9.5, dashed=True) s.wire("CTRL", [(c+190,Y["cc"]),(c+290,Y["cc"])], "one PD owner — OI-12", dy=-4, fs=6.8, arrow="both") s.block("BRC", c+290, 224, 180, 150, "ASM2464PD USB4 bridge (Pro)", ["USB4 40 Gb/s device, UAS fallback;", "PCIe side → PU-W-104"], [("L", Y["d"]-224, "d", None), ("L", Y["ss1"]-224, "ss1", None), ("L", Y["ss2"]-224, "ss2", None), ("L", Y["sbu"]-224, "sbu", None)], title_fs=9.5, dashed=True) s.wire("HS", [(c+190,Y["d"]),(c+290,Y["d"])], "USB 2.0", dy=-4, fs=6.8, arrow="both") s.wire("HS", [(c+190,Y["ss1"]),(c+290,Y["ss1"])], "USB4 lane 0 · 85 Ω L3 ≤ 60 mm", dy=-4, fs=6.8, arrow="both") s.wire("HS", [(c+190,Y["ss2"]),(c+290,Y["ss2"])], "USB4 lane 1 · TVS ≤ 0.2 pF", dy=-4, fs=6.8, arrow="both") s.wire("CTRL", [(c+190,Y["sbu"]),(c+290,Y["sbu"])], "USB4 sideband · TPD1E10B06", dy=-4, fs=6.8, arrow="both") # ================= RJ45 ================= py = [560, 590, 620, 650] s.block("J7", 60, 480, 170, 240, "J7 — RJ45 5GBASE-T", ["shielded, tab-down, no magnetics", "(Amphenol RJHSE-5380 class)", "hinged TPU door — IP54 closed"], [("R", py[0]-480, "p1", "pins 1, 2"), ("R", py[1]-480, "p2", "pins 3, 6"), ("R", py[2]-480, "p3", "pins 4, 5"), ("R", py[3]-480, "p4", "pins 7, 8"), ("R", 690-480, "sh", "shield")], title_fs=10.5, port_fs=7.5) s.label(145, 735, "cable W-16 → Cat 6A patch cable · 5GBASE-T", 7, "middle", "#1f4e9c") s.block("MAG", 330, 500, 170, 180, "Discrete 5GBASE-T magnetics", ["Pulse H5007NL class · 2 kV isolation", "≤ 15 mm from the jack, chassis side (L1)"], [("L", py[0]-500, "a1", None), ("L", py[1]-500, "a2", None), ("L", py[2]-500, "a3", None), ("L", py[3]-500, "a4", None), ("R", py[0]-500, "b1", None), ("R", py[1]-500, "b2", None), ("R", py[2]-500, "b3", None), ("R", py[3]-500, "b4", None), ("B", 85, "bs", None)], title_fs=9.5) s.block("PHY", 610, 500, 160, 180, "RTL8126 5GbE MAC + PHY", ["Gen3 ×1 on the ASM2812", "shield can; TVS TPD4E1B06 chip-side"], [("L", py[0]-500, "m0", "MDI0±"), ("L", py[1]-500, "m1", "MDI1±"), ("L", py[2]-500, "m2", "MDI2±"), ("L", py[3]-500, "m3", "MDI3±")], title_fs=9.5, port_fs=7.5) for i,y in enumerate(py): s.wire("HS", [(230,y),(330,y)], "pair %d · 100 Ω" % (i+1) if i==0 else None, dy=-4, fs=6.8) s.wire("HS", [(500,y),(610,y)], "≤ 25 mm · 100 Ω" if i==0 else None, dy=-4, fs=6.8) s.label(280, 668, "T568 pairs 1-2 / 3-6 / 4-5 / 7-8", 6.8, "middle", "#1f4e9c") s.label(280, 678, "(public standard; all four used)", 6.8, "middle", "#1f4e9c") s.wire("BOND", [(415,680),(415,702)]); s.gnd(415, 702, chassis=True) s.label(432, 712, "Bob Smith: 75 Ω + 1 nF / 2 kV", 6.8, fill="#4c7c1c"); s.label(432, 722, "on centre taps → chassis GND", 6.8, fill="#4c7c1c"); s.label(432, 732, "(not logic GND, 09 §6)", 6.8, fill="#4c7c1c") s.line("REFERENCE", 555, 498, 555, 725, "#9c1f1f", LW["fine"], "5 3") s.label(555, 492, "2 mm isolation moat, all layers (09 §6)", 6.8, "middle", "#9c1f1f") s.wire("BOND", [(230,690),(270,690)]); s.gnd(270, 690, chassis=True) s.label(287, 694, "jack frame riveted to chassis wall · W-19", 6.8, fill="#4c7c1c") # ================= M.2 Key-E ================= kx, ky = 1010, 480 s.block("J8", kx, ky, 160, 170, "J8 — M.2 Key-E 2230 socket", ["WIFI module MT7925 mated · W-11", "chassis-pressed Al / Zn-Ni standoff"], [("L", 24, "pcie", None), ("L", 52, "sb", None), ("L", 80, "usb", None), ("L", 110, "v33", None), ("R", 50, "ant0", "ANT0 MHF4"), ("R", 115, "ant1", "ANT1 MHF4")], title_fs=9.5, port_fs=7.5) s.wire("HS", [(990,ky+24),(kx,ky+24)]); s.tag(990, ky+24, "pcie2x1l1 Gen2 ×1 + REFCLK ← RK3588 SoM", "L", 6.8) s.wire("CTRL", [(990,ky+52),(kx,ky+52)]); s.tag(990, ky+52, "PERST# / CLKREQ# / W_DISABLE# ← SoM / EC", "L", 6.8) s.wire("HS", [(990,ky+80),(kx,ky+80)]); s.tag(990, ky+80, "USB 2.0 ← RK3588 USB2 host (BT held in reset)", "L", 6.8) s.wire("POWER", [(990,ky+110),(kx,ky+110)]); s.tag(990, ky+110, "3.3 V LOGIC via LC π filter · P-22", "L", 6.8) s.block("ANTW0", 1340, ky+30, 190, 40, "ANTW0 — Wi-Fi flex element", ["front frame upper band, X 12–52"], [("L", 0.5, "in", None)], title_fs=9) s.block("ANTW1", 1340, ky+95, 190, 40, "ANTW1 — Wi-Fi flex element", ["front frame upper band, X 130–170"], [("L", 0.5, "in", None), ("B", 0.5, "sh", None)], title_fs=9) s.wire("RF", [(kx+160,ky+50),(1340,ky+50)], "W-05 · MHF4 1.37 mm coax ≈ 140–150 mm", dy=-5, fs=6.8) s.wire("RF", [(kx+160,ky+115),(1340,ky+115)], "W-06 · MHF4 coax ≈ 60 mm", dy=-5, fs=6.8) s.label(1255, ky+62, "≤ 0.35 dB at 6 GHz", 6.5, "middle", "#9c1f1f"); s.label(1255, ky+127, "≤ 0.15 dB at 6 GHz", 6.5, "middle", "#9c1f1f") s.wire("BOND", [(1435,ky+135),(1435,ky+150)]); s.gnd(1435, ky+150, chassis=True) s.label(1340, ky+180, "W-21: coax shield → chassis ≤ 10 mm from each element", 6.5, fill="#4c7c1c") s.label(1180, ky+197, "Coax along the chassis top rail, clipped every 30 mm; ≥ 10 mm from buck inductors,", 6.8, fill="#333") s.label(1180, ky+208, "≥ 5 mm from LPDDR; never into the end caps (07 §4.3). MHF4 ≈ 30 mating cycles.", 6.8, fill="#333") s.label(1180, ky+222, "09 §4.2 targets antenna cables ≤ 120 mm; 07 §4.3 gives WIFI0 ≈ 140–150 mm — reconcile at EVT.", 6.8, fill="#9c1f1f") # ================= M.2 M-key ================= mx, my = 1010, 720 s.block("J9", mx, my, 160, 110, "J9 — M.2 M-key 2280 socket", ["NVMe SSD mated on Pro · W-12", "socket fitted, module absent on Base"], [("L", 24, "pcie", None), ("L", 52, "sb", None), ("L", 88, "v33", None)], title_fs=9.5, dashed=True) s.wire("HS", [(990,my+24),(mx,my+24)]); s.tag(990, my+24, "PCIe Gen3 ×2 + REFCLK ← ASM2812 downstream", "L", 6.8) s.wire("CTRL", [(990,my+52),(mx,my+52)]); s.tag(990, my+52, "PERST# / CLKREQ# ← ASM2812 / EC (TBD)", "L", 6.8) s.wire("POWER", [(990,my+88),(mx,my+88)]); s.tag(990, my+88, "3.3 V via 2.5 A eFuse from 3.3 V SLOTS · P-16", "L", 6.8) s.label(1180, my+30, "Thermal pad from the module to the magnesium skin (rear-facing socket, 09 §1.1);", 6.8, fill="#333") s.label(1180, my+41, "alternative supply: separate 3 A buck — EVT decision (05 §3.2).", 6.8, fill="#333") # ================= notes ================= s.notes(60, 752, 740, "Notes", [ "USB-C receptacles: same IP67 mid-mount part on all three ports (Amphenol / JAE DX07 IPX7 class); the receptacle nose seals with an O-ring against a moulded collar and the shell is screwed to a 1.5 mm Zn-Ni-plated steel or aluminum bracket — never stainless into magnesium (D4). The bracket, not the PCB, takes cable side-load (08 §7, 09 §11).", "Mid-mount receptacles need a board cutout; the cutout edges are plated and grounded so the L2 reference stays continuous under the SuperSpeed escape (09 §11). Each shell bonds to the chassis through its bracket and to board GND at the connector — one bond point per connector (09 §6), W-19.", "Port C: a sealed, USB4-rated receptacle is not yet sourced (09 §13); fallback is an unsealed USB4 receptacle with a moulded silicone boot (mechanical change). On Base the hole is filled with a bonded TPU plug; the receptacle stays fitted for tooling commonality (10 BOM).", "SuperSpeed plug-orientation handling (RK3588 USBDP PHY lane select vs external SS mux on Ports A/B) is not stated in any document — OI-13. Both TX/RX pair sets are wired to the receptacle as the Type-C spec requires.", "ESD / TVS classes (09 §5.3): SS pairs ≤ 0.3 pF 4-ch (TPD4E05U06 / RClamp0524P class); USB4 port ≤ 0.2 pF (TPD4E02B04 class); CC and SBU TPD1E10B06 class, 22 V-tolerant on CC; VBUS TVS 24 V standoff + OVP 22 V; D± TPD2E001; RJ45 TPD4E1B06 on the chip side of the magnetics.", "RJ45: T568 pair assignment is the public standard; 5GBASE-T (IEEE 802.3bz) uses all four pairs; PoE-in is not supported; intra-pair skew ≤ 50 ps (09 §12 item 8). Discrete magnetics because the jack needs a chassis-anchored shroud and gasket (09 §3.5).", "M.2 sockets: 75-position, 4.2 mm; pin numbers per the PCI-SIG M.2 specification are not reproduced here. Wi-Fi module antenna connectors face the board edge nearest the front-frame antennas (09 §4.2); the 3.3 V LOGIC feed to the Key-E slot carries an LC π filter for < 20 mVpp ripple (05 §5).", ], 7.4) s.titleblock() return s.write()