wiring/src/w201.py
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from sheet import Sheet, STYLE, LW, wrapimport model def cls_of(name): n = name.lower() if "lane" in n or "refclk" in n: return "HS" if n.startswith("3.3 v") or n.startswith("1.8 v"): return "POWER" if "i²c" in n: return "BUS" if n == "gnd": return "REF" return "CTRL" def rng(p): a = p.replace("–","-").split("-") return (int(a[0]), int(a[-1])) def draw(): s = Sheet("201", model.SHEETS[5][1]) x0,y0,x1,y1 = s.frame s.heading(x0+20, y0+26, "MEZZANINE CONNECTION DIAGRAM — W-01: MB J3 (Samtec ADM6, male, 80 pos.) ↔ RB J6 (Samtec ADF6, female) — logical allocation per docs/09 §8.1, NTS", 12.5) PITCH = 17; Y0 = 108 panels = [52, 800] # panel headers for k,X in enumerate(panels): s.label(X+222, 84, f"MB J3 — main-board side", 9, "middle", "#111", bold=True) s.label(X+222, 96, f"pins {1+40*k}–{40+40*k}", 8, "middle", "#333") s.label(X+526, 84, f"RB J6 — reader-board side", 9, "middle", "#111", bold=True) s.label(X+526, 96, f"pins {1+40*k}–{40+40*k}", 8, "middle", "#333") s.label(X+95, 96, "MB source / destination", 8, "middle", "#555", italic=True) s.label(X+650, 96, "RB destination / source", 8, "middle", "#555", italic=True) s.label(X+374, 96, "signal group · pins · (n) class", 8, "middle", "#555", italic=True) # connector bodies s.rect("EQUIPMENT", X+200, Y0-4, 44, 40*PITCH+8, "#f2f2f2", "#222", LW["primary"], 2) s.rect("EQUIPMENT", X+504, Y0-4, 44, 40*PITCH+8, "#f2f2f2", "#222", LW["primary"], 2) for i in range(40): p = 1+40*k+i; y = Y0 + i*PITCH + PITCH/2 s.line("EQUIPMENT", X+200, y-PITCH/2, X+244, y-PITCH/2, "#bbb", LW["hatch"]) s.line("EQUIPMENT", X+504, y-PITCH/2, X+548, y-PITCH/2, "#bbb", LW["hatch"]) s.text("EQUIPMENT", X+222, y+3, str(p), 7.2, "middle", "#333") s.text("EQUIPMENT", X+526, y+3, str(p), 7.2, "middle", "#333") # groups counts = {} for pins, name, n, mbside, rbside, note in model.MEZZ_PINS: a,b = rng(pins); c = cls_of(name); counts[c] = counts.get(c,0)+n k = 0 if a <= 40 else 1; X = panels[k] ya = Y0 + ((a-1)%40)*PITCH; yb = Y0 + ((b-1)%40+1)*PITCH st = STYLE[c] for p in range(a, b+1): y = Y0 + ((p-1)%40)*PITCH + PITCH/2 s.wire(c, [(X+244, y), (X+294, y)]); s.wire(c, [(X+454, y), (X+504, y)]) # label box s.rect("ANNOTATION", X+294, ya+1, 160, yb-ya-2, "#fff", st["stroke"], LW["fine"], 2) lab = f"{pins} · {name}" lines = wrap(lab, 152, 8) tail = f"({n}) {c}" + (f" · {note}" if note and n >= 4 else "") lines += wrap(tail, 152, 7.2) h = yb-ya; lh = 9.6; total = len(lines)*lh if total > h-2: # too tall: drop note, then shorten lines = wrap(lab, 152, 8) + [f"({n}) {c}"] total = len(lines)*lh if total > h-2: lines = wrap(f"{pins} · {name} ({n})", 152, 7.6); total = len(lines)*lh yy = ya + (h-total)/2 + lh*0.8 for i,l in enumerate(lines): s.text("ANNOTATION", X+374, yy, l, 8 if i < len(lines)-1 or len(lines)==1 else 7.2, "middle", st["stroke"] if i==0 else "#333") yy += lh # side texts for txt, xa, anchor in ((mbside, X+195, "end"), (rbside, X+553, "start")): ls = wrap(txt, 188, 7.8) if len(ls)*9.4 > h: ls = wrap(txt, 188, 7.2) tot = len(ls)*9.4; yy = ya + (h-tot)/2 + 9.4*0.8 for l in ls: s.text("ANNOTATION", xa, yy, l, 7.8, anchor, "#222"); yy += 9.4 # bracket on RB side for notes of small groups (n<4) with notes if note and n < 4: s.label(X+553+188, ya+h/2+3, "", 7) # notes + summary NY = Y0 + 40*PITCH + 14 rows = [[c, model.__dict__.get("_",None) or "", str(counts.get(c,0))] for c in ("HS","POWER","CTRL","BUS","REF")] desc = {"HS":"PCIe lanes and HCSL REFCLK pairs (CFe B Gen3/Gen4 ×2, CFe A ×1, GL9755, GL9750, ASM1064)", "POWER":"3.3 V SLOTS (8), 3.3 V LOGIC (2), 1.8 V (1)", "CTRL":"PERST# / CLKREQ# / WAKE#, PWR_EN ×5, SLOT_FAULT#, SLOT_DET[4:0], HALL, LED_DATA, NTC_CFEB, RB_PRESENT#", "BUS":"EC I²C to RB EEPROM and eFuse telemetry", "REF":"GND (9 listed pins + connector ground-pattern contacts)"} rows = [[c, desc[c], str(counts.get(c,0))] for c in ("HS","POWER","CTRL","BUS","REF")] + [["Total", "", str(sum(counts.values()))]] s.subheading(x0+20, NY+10, "PIN SUMMARY BY CLASS") s.table(x0+20, NY+16, [60, 520, 50], rows, ["Class", "Contents", "Pins"], 8, pad=3) notes = [ "Logical allocation only (09 §8.1). Physical pin numbering, the one-GND-between-pairs pattern on the high-speed rows and the ADM6/ADF6 variant (stack height, ground-pattern option) are finalised from Samtec's S-parameter model at layout and when docs/08 fixes the RB-to-MB spacing (09 §13).", "CFe B pairs (pins 1–8) form the Gen4 mux path: RB trace ≤ 40 mm on L3 with one reference plane each side and no layer change except the connector escape; mezzanine budget ≈ 0.5 dB at 8 GHz (09 §2.2, §3.2). Crosstalk target NEXT/FEXT ≤ −30 dB to 8 GHz (09 §12 item 6).", "3.3 V SLOTS on 8 pins (44–51) for ≥ 6 A total at a derated 0.75 A/pin (0.635 mm pitch). Slot eFuses and their card-detect gating sit on the RB; the eFuse limits differ between docs/05 and docs/09 (OI-2).", "OI-9: the mode-switch interlock (74LVC1G373, 09 §5.4) wants CFEB_PWR_EN_SENSE from the CFe B eFuse power-good, but no PG / sense return pin exists in this allocation — only the wired-OR SLOT_FAULT# (60). Add a pin or sense the EC's CFEB_PWR_EN on the MB (see PU-W-104).", "OI-4: HALL (66) assumes the Hall sensor is on the RB; docs/09 §9.1 also names a 'Button/Hall flex' on MB J11. One location must be chosen. LED_DATA (67) drives the RB LED bar (J7); the bar's supply rail is not a mezzanine rail (OI-15).", "GND (72–80) is the listed count; the Samtec ground contacts in the shield / rows are additional and depend on the variant — confirm against the connector drawing at schematic capture.", ] s.notes(x0+700, NY+4, 800, "Notes", notes, 8) s.titleblock() return s.write()