wiring/src/w104.py
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from sheet import Sheet, STYLE, LWimport model def draw(): s = Sheet("104", model.SHEETS[4][1]) s.heading(60, 66, "CFEXPRESS B MODE-SWITCH PATH — lane mux, REFCLK mux, hardware interlock, USB4 bridge, Port C", 14) s.label(60, 81, "Logical wiring, NTS. MB = main board, RB = reader daughterboard, EC = nRF5340. Pro-only population dashed (ASM2464PD, TPS25750-C, TPS2121-class mux). Sources: docs/02 §4.2, §6, §8; docs/09 §3.2, §4.1, §5.2, §5.4, §8.1.", 8.5, fill="#333") LAN, REF, V33, PWR, DET, NTC, PER, CLK, GND = 142, 172, 245, 412, 437, 462, 500, 525, 565 # ---------------- SoM ---------------- s.block("SOM", 120, 96, 180, 118, "RK3588 SoM (J1/J2) — D12", None, [("R", LAN-96, "lanes", "pcie3x4 lane 0/1 TX/RX"), ("R", REF-96, "refclk", "REFCLK 100 MHz HCSL"), ("L", 158-96, "perstreq", "SOC_CFEB_PERST_REQ#"), ("L", 176-96, "odin", "CLKREQ#/WAKE# in"), ("L", 194-96, "uart", "UART / I²C to EC")], port_fs=7.5) # ---------------- mux ---------------- s.block("MUX", 380, 96, 180, 190, "PI3DBS16412 2:1 ×2 lane mux", None, [("L", LAN-96, "Al", "A: SoC lanes"), ("L", REF-96, "Ar", "A: SoC REFCLK"), ("L", 230-96, "Bl", "B: bridge lanes"), ("L", 255-96, "Br", "B: bridge REFCLK"), ("R", LAN-96, "Cl", "COM lanes"), ("R", REF-96, "Cr", "COM REFCLK"), ("B", 70, "sel", None), ("R", 276-96, "rsel", "REFCLK_SEL")], port_fs=7.5) for i,t in enumerate(["16 GT/s passive differential switch (2 lanes)", "+ HCSL 2:1 REFCLK mux (PI6C59S6005 class)", "SEL common to both, driven by the latch Q"]): s.label(470, 196+i*11, t, 7.2, "middle", "#333") s.wire("HS", [(300,LAN),(380,LAN)], "4 pairs Gen3", dy=-5, fs=7) s.wire("HS", [(300,REF),(380,REF)], "HCSL 100 Ω", dy=9, fs=7) s.wire("HS", [(560,LAN),(680,LAN)], "4 pairs · L3 ≤ 30 mm", dy=-5, fs=7) s.wire("HS", [(560,REF),(680,REF)], "REFCLK+/− (mux out)", dy=9, fs=7) # ---------------- latch ---------------- s.block("LATCH", 380, 296, 160, 56, "74LVC1G373 transparent latch", ["LE = NOT CFEB_PWR_EN_SENSE"], [("B", 40, "D", None), ("L", 0.6, "LE", None), ("T", 70, "Q", None)], title_fs=9.5, port_fs=7.5) s.circle("EQUIPMENT", 377, 330, 3.2, "#fff", "#222", 1.2) s.wire("REF", [(374,330),(340,330)], arrow="start"); s.tag(338, 330, "OI-9", "L", 7) s.wire("CTRL", [(450,296),(450,286)]) s.label(456, 292, "Q → SEL (held while slot powered)", 7, fill="#1b7a3a") # ---------------- EC ---------------- s.block("EC", 400, 366, 200, 274, "nRF5340 EC", None, [("T", 40, "muxsel", None), ("T", 172, "rsel", None), ("L", 400-366, "brperst", "BR_CFEB_PERST# in"), ("L", 425-366, "odbr", "CLKREQ#/WAKE# → bridge (2× OD)"), ("L", 455-366, "aspwr", "ASM2464_PWR_EN"), ("R", PWR-366, "pwren", "CFEB_PWR_EN"), ("R", DET-366, "det", "SLOT_DET[0]"), ("R", NTC-366, "ntc", "NTC_CFEB (ADC)"), ("R", PER-366, "perst", "CFEB_PERST#"), ("R", CLK-366, "clkreq", "CFEB_CLKREQ#/WAKE# in"), ("B", 90, "sperst", None), ("B", 110, "sod", None), ("B", 130, "suart", None)], port_fs=7.5) s.label(500, 570, "Single owner of every CFe B reset, clock-request", 7.2, "middle", "#333") s.label(500, 581, "and select line; sidebands never pass the mux (02 §6.1)", 7.2, "middle", "#333") s.wire("CTRL", [(420,366),(420,352)]); s.label(426, 362, "MUX_SEL → D", 7, fill="#1b7a3a") s.wire("REF", [(552,366),(552,358),(600,358),(600,276),(560,276)], arrow="end") s.label(604, 318, "REFCLK_SEL", 6.4, fill="#777"); s.label(604, 327, "(test pin; = MUX_SEL)", 6.4, fill="#777") # EC ↔ J3 rows s.wire("CTRL", [(600,PWR),(680,PWR)], "pin 55", dy=-4, fs=7, arrow="end") s.wire("CTRL", [(680,DET),(600,DET)], "pin 61", dy=-4, fs=7, arrow="end") s.wire("CTRL", [(680,NTC),(600,NTC)], "pin 70 (analog)", dy=-4, fs=7, arrow="end") s.wire("CTRL", [(600,PER),(680,PER)], "pin 11", dy=-4, fs=7, arrow="end") s.wire("CTRL", [(680,CLK),(600,CLK)], "pins 12–13", dy=-4, fs=7, arrow="end") # ---------------- bridge ---------------- s.block("BR", 120, 330, 180, 170, "ASM2464PD USB4↔PCIe bridge", ["Pro SKU only — depopulated on Base (D7)", "Gen4 ×2 to the card; USB4 40 Gb/s or", "USB 3.2 Gen2 UAS fallback to the host"], [("T", 40, "bl", None), ("T", 90, "br", None), ("R", 400-330, "perst", "BR_CFEB_PERST# out"), ("R", 425-330, "od", "CLKREQ#/WAKE# in"), ("R", 455-330, "en", "ASM2464_PWR_EN (load-sw. EN)"), ("R", 485-330, "v33", "3.3 V in"), ("B", 30, "usb4", None), ("B", 90, "sbu", None), ("B", 140, "d", None)], dashed=True, title_fs=10.5, port_fs=7.5) s.label(163, 322, "Gen4 ×2", 7, "middle"); s.label(213, 322, "REFCLK out", 7, "middle") s.wire("HS", [(160,330),(160,230),(380,230)], "4 pairs Gen4 · L3 ≤ 50 mm · 220 nF AC caps at TX", seg=1, dy=-5, fs=7) s.wire("HS", [(210,330),(210,255),(380,255)], "bridge downstream REFCLK", seg=1, dy=9, fs=7) s.wire("CTRL", [(300,400),(400,400)], arrow="end") s.wire("CTRL", [(400,425),(300,425)], arrow="end") s.wire("CTRL", [(400,455),(300,455)], arrow="end") s.wire("POWER", [(300,485),(304,485)]); s.tag(304, 485, "3.3 V LOGIC via load sw. · P-21", "R", 6.8) # ---------------- Port C ---------------- s.block("PC", 120, 540, 180, 110, "J6 — Port C USB-C 'USB4 FAST'", ["IP67 mid-mount, USB4-rated receptacle", "fitted on both SKUs, blanked on Base", "cable W-15 → USB4 host / PD source"], [("T", 30, "usb4", None), ("T", 90, "sbu", None), ("T", 140, "d", None), ("B", 40, "cc", None), ("B", 140, "vbus", None)], title_fs=10.5, port_fs=7.5) s.wire("HS", [(150,500),(150,540)]); s.wire("HS", [(210,500),(210,540)]); s.wire("HS", [(260,500),(260,540)]) s.label(268, 517, "USB4 TX1/RX1 TX2/RX2 · SBU1/2 · D±", 6.8, fill="#1f4e9c") s.label(268, 528, "≤ 60 mm Megtron 6, ≤ 4 dB at 10 GHz", 6.5, fill="#1f4e9c") s.block("PDC", 120, 690, 180, 60, "TPS25750-C — PD sink (Pro)", None, [("T", 40, "cc", None), ("R", 0.55, "att", "PORTC_ATTACH / PD_PRESENT"), ("R", 0.85, "i2c", "PD_I2C")], dashed=True, title_fs=10, port_fs=7) s.label(210, 762, "owns CC1/CC2; ASM2464PD PD block passive (00 §3.4) — verify, OI-12", 6.8, "middle", "#9c1f1f") s.wire("CTRL", [(160,650),(160,690)]); s.label(166, 673, "CC1 / CC2", 7, fill="#1b7a3a") s.wire("POWER", [(260,650),(260,670),(300,670)], arrow="end"); s.tag(303, 670, "VBUS → TPS2121 mux · P-02", "R", 7) s.wire("CTRL", [(300,723),(340,723)]); s.tag(343, 723, "→ EC", "R", 7) s.wire("BUS", [(300,741),(340,741)]); s.tag(343, 741, "↔ EC", "R", 7) # ---------------- SoM ↔ EC snake ---------------- s.wire("CTRL", [(120,158),(75,158),(75,792),(470,792),(470,640)], "SOC_CFEB_PERST_REQ# — SoC root-port PERST request; the EC mirrors it to the slot in standalone mode (< 1 ms)", seg=2, dy=-5, fs=7, arrow="end") s.wire("CTRL", [(490,640),(490,808),(85,808),(85,176),(120,176)], "CFEB_CLKREQ# / CFEB_WAKE# → SoC (2× open-drain from the EC, only while the SoC owns the card)", seg=1, dy=-5, fs=7, arrow="end") s.wire("BUS", [(120,194),(95,194),(95,824),(510,824),(510,640)], "EC_SOC_UART / I²C — HOST_C_ATTACH, CFEB_RELEASED, CFEB_RETURNED, MODE_READER_C (02 §6.3)", seg=2, dy=-5, fs=7, arrow="both") # ---------------- J3 / J6 mezzanine ---------------- jx, jy, jw, jh = 680, 96, 150, 490 rows = [(LAN,"1–8","CFe B lanes"),(REF,"9–10","REFCLK"),(V33,"44–51","3.3 V SLOTS"),(PWR,"55","CFEB_PWR_EN"),(DET,"61","SLOT_DET[0]"),(NTC,"70","NTC_CFEB"),(PER,"11","PERST#"),(CLK,"12–13","CLKREQ#/WAKE#"),(GND,"72–80","GND ×9 + pattern")] ports = [] for y,p,_ in rows: ports += [("L", y-jy, "L"+p, p), ("R", y-jy, "R"+p, p)] s.block("J3J6", jx, jy, jw, jh, "J3 ↔ J6", ["ADM6 (MB) / ADF6 (RB) 80-pin · W-01"], ports, port_fs=7.5) s.line("EQUIPMENT", jx+jw/2, jy+34, jx+jw/2, jy+jh, "#555", LW["fine"], "4 3") for y,p,name in rows: s.label(jx+jw/2, y-7, name, 6.6, "middle", "#333") s.tag(586, V33, "3.3 V SLOTS · P-15", "R", 7); s.wire("POWER", [(672,V33),(680,V33)]) # ---------------- RB region ---------------- s.rect("REFERENCE", 842, 86, 696, 522, "none", "#888", LW["fine"], 4, 'stroke-dasharray="6 4"') s.label(850, 100, "RB — reader daughterboard (mated to the MB via J3/J6, W-01)", 8, fill="#555") s.block("SLOT", 1300, 100, 220, 450, "J1 — CFexpress Type B slot", None, [("L", LAN-100, "lanes", "PCIe lane 0/1 TX/RX"), ("L", REF-100, "refclk", "REFCLK"), ("L", V33-100, "v33", "3.3 V"), ("L", DET-100, "cd", "card-detect"), ("L", PER-100, "perst", "PERST#"), ("L", CLK-100, "clkreq", "CLKREQ# / WAKE#")], port_fs=7.5) for i,t in enumerate(["push-push, deep insertion, metal cage, 10 k cycles", "card = NVMe; Gen3 ×2 to SoC / Gen4 ×2 to bridge", "TVS ≤ 0.3 pF on lane pairs + CLKREQ#/PERST#", "AC caps: the card carries its TX caps; ours sit", "at the mux inputs from SoC and bridge (09 §4)", "cage: Cu pour + 40 thermal vias → pad → rib"]): s.label(1410, 285+i*11, t, 7.2, "middle", "#333") s.wire("HS", [(830,LAN),(1300,LAN)], "4 pairs · RB L3 straight run ≤ 40 mm · Gen4-capable · whole mux path ≤ 120 mm, ≤ 8 dB at 8 GHz (09 §3.2)", dy=-5, fs=7) s.wire("HS", [(830,REF),(1300,REF)], "REFCLK+/− 100 Ω HCSL", dy=9, fs=7) s.block("EF", 920, 200, 190, 90, "eFuse TPS2596 class — CFe B", ["limit 2.5 A (09 §5.2) / 2.0 A (05 §3.2) — OI-2", "soft-start 1–2 ms, reverse-current block,", "active discharge · FLT# → SLOT_FAULT# (pin 60)"], [("L", 0.5, "in", None), ("R", 0.5, "out", None), ("B", 80, "en", None)], title_fs=10, port_fs=7.5) s.wire("POWER", [(830,V33),(920,V33)]) s.wire("POWER", [(1110,V33),(1300,V33)], "3.3 V slot rail (per-slot island, 47 µF)", dy=-5, fs=7) s.block("AND", 970, 320, 60, 44, "&", None, [("L", 0.5, "a", None), ("R", 0.5, "b", None), ("T", 0.5, "y", None)], title_fs=13) s.wire("CTRL", [(1000,320),(1000,290)]); s.label(1006, 308, "EN", 7, fill="#1b7a3a") s.wire("CTRL", [(830,PWR),(900,PWR),(900,342),(970,342)], "CFEB_PWR_EN", seg=0, dy=-4, fs=7, arrow="end") s.wire("CTRL", [(1300,DET),(830,DET)], "card-detect → SLOT_DET[0] (EC wake); slot powered only with a card present (09 §5.2)", dy=-4, fs=7, arrow="end") s.junction("CTRL", 1060, DET); s.wire("CTRL", [(1060,DET),(1060,342),(1030,342)], arrow="end") s.block("NTC", 1140, 447, 150, 32, "NTC 10 k — CFe B cage", None, [("L", 0.5, "o", None)], title_fs=9) s.wire("CTRL", [(1140,463),(1140,NTC),(830,NTC)], arrow="end") s.wire("CTRL", [(830,PER),(1300,PER)], "CFEB_PERST# — driven by the EC; follows the SoC's request or the bridge's PERST by mode", dy=-4, fs=7, arrow="end") s.wire("CTRL", [(1300,CLK),(830,CLK)], "CFEB_CLKREQ# / CFEB_WAKE# from the slot → EC → forwarded to the active root (SoC or bridge)", dy=9, fs=7, arrow="end") # ---------------- mode table + notes ---------------- s.subheading(850, 640, "Hardware routing by mode (docs/02 §6.1)", 9.5) rows = [ ["PI3DBS16412 lanes", "A: SoC pcie3x4 ↔ slot", "B: ASM2464PD ↔ slot"], ["REFCLK mux", "SoC root REFCLK → slot", "ASM2464PD REFCLK → slot"], ["CFEB_PERST#", "EC, follows SOC_CFEB_PERST_REQ#", "EC, follows BR_CFEB_PERST#"], ["CLKREQ# / WAKE# from slot", "EC → SoC (open-drain)", "EC → ASM2464PD (open-drain)"], ["CFEB_PWR_EN (slot eFuse)", "on", "on, after the mux settles"], ["ASM2464_PWR_EN", "off — bridge unpowered, zero draw", "on"], ["Port C VBUS → charger (Pro)", "mux passes Port A only", "Port C OR-ed via TPS2121; Port A wins"], ["NVMe namespace write-protect", "WPS = 0", "WPS = 1 set by SoC before release (D8)"], ] yb = s.table(850, 648, [190, 240, 250], rows, ["Element", "Standalone", "Port C host mode"], 7.8, pad=3) s.notes(850, yb+10, 680, "Notes", [ "SoC → mux A: Gen3 (8 GT/s) on L5 FR-4, ≤ 100 mm; mux → J3: MB L3 Megtron 6 ≤ 30 mm; RB ≤ 40 mm (09 §3.2). Card-side REFCLK: 100 Ω HCSL, 33 Ω series + 49.9 Ω shunt at the source, ≤ 0.5 ps RMS additive jitter through the mux (09 §4.1).", "Interlock (09 §5.4): D = EC MUX_SEL, LE = NOT CFEB_PWR_EN_SENSE, Q → both SEL pins — an unintended flip with a live card is impossible regardless of EC firmware. OI-9: 09 §5.4 takes the sense from the eFuse power-good, but that eFuse is on the RB and the 09 §8.1 mezzanine allocation has no PG return pin.", "ASM2464PD: 3.3 V LOGIC through a load switch (EN = ASM2464_PWR_EN), 1.05 V point-of-load buck ≤ 15 mm, SPI flash for its firmware; USB4 pairs to J6 use a ≤ 0.2 pF TVS (09 §5.1, §5.3). Base SKU: ASM2464PD, TPS25750-C and the TPS2121-class mux are depopulated; J6 is fitted and blanked and its VBUS pin goes only to attach detection (05 §7.5).", ], 7.5, numbered=False) s.notes(60, 836, 740, "Entering Port C host mode — EC-sequenced (docs/02 §6.3; target: card visible to the host in < 5 s)", [ "Port C attach: TPS25750-C → PORTC_ATTACH → EC → UART HOST_C_ATTACH → SoC (≤ 50 ms). Pro: the Mac's VBUS is accepted at the charger through the priority mux from this moment.", "SoC finishes the current part, checkpoints, fsyncs the job DB (≤ 1000 ms); unmounts the RO filesystem; Set Features 0x84 WPS = 1 if the card reports NWPC (≤ 50 ms) — else bridge WP (UAS) or user consent before flipping (02 §4.10).", "SoC removes the PCI device, root port → D3, UART CFEB_RELEASED (≤ 400 ms; t ≤ 1500 ms cumulative).", "EC: CFEB_PERST# low → CFEB_PWR_EN off, 200 ms dwell (active discharge, card < 0.3 V within 150 ms) → MUX_SEL = B, REFCLK_SEL = B (latch open while unpowered; 10 ms).", "EC: ASM2464_PWR_EN on → bridge boots from SPI flash (300–500 ms) → CFEB_PWR_EN on, 100 ms → CFEB_PERST# released, now following BR_CFEB_PERST#.", "Bridge trains Gen4 ×2 (≤ 300 ms); USB4 tunnel or USB 3.2 UAS enumeration; host mounts (1000–2000 ms); EC → SoC MODE_READER_C. Total ≈ 3.5–4.5 s. Exit reverses (02 §6.4): PERST# low, PWR_EN off 200 ms, bridge off, MUX_SEL = A, PWR_EN on, CFEB_RETURNED, SoC clears WPS, remounts RO.", ], 7.5) s.titleblock() return s.write()