wiring/src/w103.py
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from sheet import Sheet, STYLE, LWimport model def draw(): s = Sheet("103", model.SHEETS[3][1]) x0,y0,x1,y1 = s.frame s.heading(x0+20, y0+30, "EMBEDDED-CONTROLLER (nRF5340) CONTROL AND SENSOR WIRING — signal owner view, NTS", 14) s.label(x0+20, y0+46, "Every line is a main-board trace unless it ends at a connector (J3 mezzanine, J10, J11, J12, J14, TP-THSW). Signal names per docs/02 §8. Arrowheads show signal direction; none = bidirectional bus.", 8.5, fill="#333") PITCH = 16 # ----- geometry ------------------------------------------------------------------------- LX, LW_, RX, RW = x0+50, 300, x1-350, 300 # left / right far-end blocks EX, EW = 640, 300 # EC block EY = 110 # far-end blocks: (bid, title, sub, y, [(pid, far_label, ec_label, cls, dir, wire_label, n)]) # dir: "out" EC→far, "in" far→EC, "bi" left = [ ("SOM", "RK3588 SoM (via J1/J2 B2B, W-10)", ["board-down RK3588J: same signals, no J1/J2 (D12)"], 110, [ ("uart", "SoC UART", "EC_SOC_UART_TX/RX", "BUS", "bi", "UART 1 Mbaud, CRC-framed", 2), ("i2c", "SoC I²C controller", "EC_SOC_I2C (EC = target)", "BUS", "bi", "I²C 400 kHz", 2), ("pmic", "RK806 PMIC enable", "PMIC_EN", "CTRL", "out", "GPIO", 1), ("rst", "SoM reset", "SOC_RESET#", "CTRL", "out", "GPIO open-drain", 1), ("hb", "heartbeat GPIO 1 Hz", "SOC_HEARTBEAT", "CTRL", "in", "watchdog 2 s", 1), ("wake", "wake input", "SOC_WAKE#", "CTRL", "out", "GPIO", 1), ("prq", "pcie3x4 PERST request", "SOC_CFEB_PERST_REQ#", "CTRL", "in", "GPIO", 1), ("fwd", "CLKREQ# / WAKE# inputs", "CFEB_CLKREQ#/WAKE# → SoC", "CTRL", "out", "2× open-drain (SoC owns card)", 2), ]), ("MSW", "CFe B mode-switch circuit", ["PI3DBS16412 lane mux · HCSL clock mux", "74LVC1G373 latch · ASM2464PD (Pro) — detail: PU-W-104"], 320, [ ("msel", "74LVC1G373 D input", "MUX_SEL", "CTRL", "out", "latched while CFEB_PWR_EN low", 1), ("rsel", "clock-mux SEL (via latch Q)", "REFCLK_SEL", "CTRL", "out", "GPIO (test pin)", 1), ("prst", "→ J3 pin 11 (slot PERST#)", "CFEB_PERST#", "CTRL", "out", "EC-combined PERST", 1), ("brp", "ASM2464PD PERST output", "BR_CFEB_PERST#", "CTRL", "in", "GPIO (Pro)", 1), ("crq", "← J3 pins 12–13 (slot)", "CFEB_CLKREQ#, CFEB_WAKE#", "CTRL", "in", "GPIO", 2), ("fwdb", "ASM2464PD CLKREQ#/WAKE#", "CFEB_CLKREQ#/WAKE# → bridge", "CTRL", "out", "2× open-drain (bridge owns card)", 2), ("bpe", "3.3 V load switch EN", "ASM2464_PWR_EN", "CTRL", "out", "GPIO (Pro)", 1), ]), ("MEZ", "J3 mezzanine → reader board (W-01)", ["80-pin ADM6/ADF6 — allocation on PU-W-201"], 520, [ ("pen", "pins 55–59 → eFuse EN", "CFEB/CFEA/SD/USD/CFAST_PWR_EN", "CTRL", "out", "5× GPIO", 5), ("flt", "pin 60 ← wired-OR FLT#", "SLOT_FAULT#", "CTRL", "in", "GPIO", 1), ("det", "pins 61–65 ← card-detect", "SLOT_DET[4:0]", "CTRL", "in", "5× GPIO interrupt / wake", 5), ("hall", "pin 66 ← Hall sensor", "HALL (baseline: RB)", "CTRL", "in", "GPIO — OI-4", 1), ("led", "pin 67 → RB J7 LED bar", "LED_DATA", "CTRL", "out", "serial LED", 1), ("rbi2c","pins 68–69 EEPROM / eFuse telemetry", "EC_I2C (RB)", "BUS", "bi", "I²C", 2), ("ntcb", "pin 70 ← NTC at CFe B cage", "NTC_CFEB", "CTRL", "in", "analog", 1), ("rbp", "pin 71 (GND on RB)", "RB_PRESENT#", "CTRL", "in", "GPIO pull-up", 1), ]), ] right = [ ("PWR", "PD controllers · charger · bucks · pack (PU-W-102)", ["TPS25750-A/-B/-C · TPS2121-class mux (Pro) · BQ25792 · 4 bucks · J12 pack"], 110, [ ("aa", "TPS25750-A", "PORTA_ATTACH", "CTRL", "in", "GPIO", 1), ("ab", "TPS25750-B", "PORTB_ATTACH", "CTRL", "in", "GPIO", 1), ("ac", "TPS25750-C (Pro)", "PORTC_ATTACH", "REF", "in", "GPIO (Pro)", 1), ("ven", "TPS2596 Port B eFuse EN", "PORTB_VBUS_EN", "CTRL", "out", "GPIO", 1), ("ilim","PD-B Rp + eFuse ILIM", "PORTB_ILIM", "CTRL", "out", "0.5 / 1.5 / 3 A (D13)", 1), ("cpd", "TPS25750-C (Pro)", "PORTC_PD_PRESENT", "REF", "in", "GPIO / I²C (Pro)", 1), ("mst", "TPS2121-class mux (Pro)", "VBUS_MUX_STAT", "REF", "in", "GPIO (Pro)", 1), ("pdi", "TPS25750 ×3 + BQ25792", "PD_I2C (EC = controller)", "BUS", "bi", "I²C", 2), ("ben", "TPS56637 · TPS62933 · LMR33640 ×2", "Buck EN ×4 / PG", "CTRL", "out", "rail sequencing", 4), ("vss", "VSYS divider", "VSYS_SENSE", "CTRL", "in", "ADC 1 kHz, brown-out < 6.2 V", 1), ("smb", "J12 pins 3–4 → BQ40Z50-R2 (W-02)", "PACK_SMBUS", "BUS", "bi", "SMBus 100 kHz", 2), ("aon", "TPS7A16 3.3 V AON LDO", "3.3 V AON supply", "POWER", "in", "≤ 120 mA, always on", 1), ]), ("SEN", "Thermal and position sensors", None, 380, [ ("ntc", "NTC 10 k ×6 (allocation: OI-8)", "NTC[5:0]", "CTRL", "in", "6× analog", 6), ("tsw", "TP-THSW ← thermal switch (W-08)", "THERM_ALERT", "CTRL", "in", "GPIO — rating 48 / 60 °C: OI-1", 1), ("hlt", "J11 pin 4 (alt. Hall on flex)", "HALL (alternative)", "REF", "in", "only if Hall moves to J11 — OI-4", 1), ]), ("UI", "User interface", None, 480, [ ("ospi","J10 → OLED module (W-03)", "OLED_SCLK, OLED_SDIN", "BUS", "out", "SPI", 2), ("octl","J10 → OLED module", "OLED_CS#, OLED_DC, OLED_RST#", "CTRL", "out", "3× GPIO", 3), ("btn", "J11 pin 2 ← button (W-04)", "BTN", "CTRL", "in", "series 1 kΩ + TVS", 1), ("rstp","MB-mounted sealed tact (assumed)", "RESET (pinhole)", "REF", "in", "GPIO — OI-14", 1), ("ledr","→ J3 pin 67 (see left)", "LED_DATA", "REF", "out", "same net as mezzanine pin 67", 1), ]), ("DBG", "Debug and radio", None, 620, [ ("swd", "J14 Tag-Connect TC2030", "EC_SWD", "BUS", "bi", "SWD — APPROTECT at PVT", 3), ("ble", "chip antenna, bottom-left corner", "BLE 5.4, 2.4 GHz", "RF", "bi", "on-board, 6 × 12 mm keep-out", 1), ]), ] # EC block: collect port ys ec_ports = [] def far_block(bid, title, sub, y, ports, x, w, side): n = len(ports); top = 44 if sub else 30 h = top + n*PITCH + 6 plist = [(side, top + i*PITCH + 6, pid, flab) for i,(pid,flab,elab,cls,d,wl,cnt) in enumerate(ports)] s.block(bid, x, y, w, h, title, sub, plist, port_fs=8) for i,(pid,flab,elab,cls,d,wl,cnt) in enumerate(ports): ec_ports.append(("L" if side=="R" else "R", y + top + i*PITCH + 6 - EY, bid+"."+pid, elab)) return y+h for bid,title,sub,y,ports in left: far_block(bid,title,sub,y,ports,LX,LW_,"R") for bid,title,sub,y,ports in right: far_block(bid,title,sub,y,ports,RX,RW,"L") EH = max(p[1] for p in ec_ports) + 20 s.block("EC", EX, EY, EW, EH, "nRF5340 EMBEDDED CONTROLLER (EC)", ["always-on domain · BLE 5.4 · owner of power sequencing,", "mode switch, thermal safety, display"], ec_ports, fill="#eef3ea", port_fs=8) # wires for blocks, far_side in ((left,"R"),(right,"L")): for bid,title,sub,y,ports in blocks: for pid,flab,elab,cls,d,wl,cnt in ports: fx,fy = s.A(bid,pid); ex,ey = s.A("EC", bid+"."+pid) assert abs(fy-ey) < 0.5 a,b = (ex,ey),(fx,fy) if d == "out": pts=[a,b]; arrow="end" elif d == "in": pts=[b,a]; arrow="end" else: pts=[a,b]; arrow="both" s.wire(cls, pts, wl, dy=-4, fs=7.8, arrow=arrow) if cnt > 1: mx = fx + (28 if far_side=="R" else -28) s.bus_tick(cls, mx, ey, cnt) # off-sheet tags near the far-end blocks s.tag(LX, 306, "PU-W-104 mode-switch detail", "R") s.tag(LX, 506, "PU-W-201 mezzanine pins", "R") s.tag(RX+RW, 96, "PU-W-102 power tree", "L") s.tag(RX+RW, 366, "PU-W-204 J10 / J11 / J12 / J14 pinouts", "L") # ----- notes and summary table -------------------------------------------------------------- ny = 748 notes = [ "The EC is the sole arbiter of mode-switch sequencing: MUX_SEL and REFCLK_SEL change only while CFEB_PWR_EN is low and CFEB_PERST# is asserted; the 74LVC1G373 latch makes this a hardware interlock independent of firmware (docs/02 §6.1, §8; docs/09 §5.4). Sideband signals PERST#/CLKREQ#/WAKE# terminate at the EC, which forwards them to the SoC or the ASM2464PD by mode.", "SOC_HEARTBEAT is a 1 Hz toggle watched with a 2 s timeout; on loss the EC completes any hand-off autonomously, then asserts SOC_RESET# (docs/02 §6.7).", "Thermal safety rule (D2, firmware): skin ≥ 52 °C, internal air ≥ 60 °C or battery ≥ 55 °C → THERMAL_PAUSE_REQ over UART, then PMIC_EN low; auto-resume at skin ≤ 42 °C and air ≤ 45 °C. THERM_ALERT from the mechanical switch is the firmware-independent backstop.", "Port B supply policy (D13): PORTB_ILIM = min(user setting, 1.5 A) on battery; 3 A only while a PD contract is present on Port A (or Port C on Pro) — ADR 00 §3.5 requires ≥ 45 W for the 3 A step; drops to 1.5 A within 500 ms of losing external power.", "Open items drawn as TBD/alternative: OI-1 thermal-switch rating and circuit; OI-4 Hall sensor on RB (mezzanine 66) vs J11 flex; OI-8 NTC channel allocation differs between docs/02, 06, 09 and 10; OI-14 reset pinhole switch has no connector or EC signal in docs/09 §9.1 / 02 §8.", "Pro-only signals (PORTC_ATTACH, PORTC_PD_PRESENT, VBUS_MUX_STAT, BR_CFEB_PERST#, ASM2464_PWR_EN) are routed on every PCB; their far-end parts are depopulated on Base.", ] s.notes(x0+20, ny, 560, "Notes", notes, 8) rows = [ ["SoM (J1/J2)", "UART, I²C, PMIC_EN, SOC_RESET#, SOC_HEARTBEAT, SOC_WAKE#, SOC_CFEB_PERST_REQ#, 2× forwarded CLKREQ#/WAKE#", "11", "BUS / CTRL", "—"], ["Mode switch", "MUX_SEL, REFCLK_SEL, CFEB_PERST#, BR_CFEB_PERST#, CFEB_CLKREQ#, CFEB_WAKE#, 2× forwarded to bridge, ASM2464_PWR_EN", "9", "CTRL", "PU-W-104"], ["Mezzanine J3", "5× PWR_EN, SLOT_FAULT#, SLOT_DET[4:0], HALL, LED_DATA, I²C ×2, NTC_CFEB, RB_PRESENT#", "17 pins (55–71)", "CTRL / BUS", "PU-W-201"], ["PD / power", "3× PORTx_ATTACH, PORTB_VBUS_EN / ILIM, PORTC_PD_PRESENT, VBUS_MUX_STAT, PD_I2C ×2, buck EN/PG ×4, VSYS_SENSE, PACK_SMBUS ×2, AON in", "≈ 17", "CTRL / BUS / POWER", "PU-W-102"], ["Sensors", "NTC[5:0], THERM_ALERT, (HALL alt.)", "7–8", "CTRL", "PU-W-204"], ["UI", "OLED SPI ×2 + CS/DC/RST, BTN, RESET, LED_DATA", "7", "BUS / CTRL", "PU-W-204"], ["Debug / radio", "SWD (SWDIO, SWCLK, nRESET, SWO), BLE chip antenna", "4 + RF", "BUS / RF", "PU-W-204"], ] s.subheading(x0+590, ny+12, "SIGNAL GROUP SUMMARY (source: docs/02 §8 table, model.EC_SIGNALS)") s.table(x0+590, ny+20, [85, 600, 70, 95, 60], rows, ["Group", "Signals", "Count", "Class", "Detail"], 7.8, pad=3) s.titleblock() return s.write()