wiring/src/w102.py
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from sheet import Sheet, LW, STYLEimport model def draw(): s = Sheet("102", model.SHEETS[2][1]) x0,y0,x1,y1 = s.frame s.heading(x0+20, y0+30, "POWER DISTRIBUTION WIRING — inputs, charger, pack, rails, consumers (main board unless noted)", 14) s.label(x0+20, y0+46, "Logical wiring, NTS. Rail names and ratings from docs/05 §3–5 and docs/09 §5.1; link IDs P-nn are tabulated in PU_Connection-Schedule_Rev-A.md. Dashed blocks: Pro-only population (same PCB).", 8.5, fill="#333") # ---------------- inputs ---------------- s.block("J4", 60,105,140,70, "J4 Port A USB-C", ["IP67 mid-mount · 'PD / PHONE'", "sink ≤ 100 W · source 1.5 A"], [("R",0.66,"VBUS","VBUS"),("R",0.9,"CC","CC1/CC2")], port_fs=8) s.block("J6", 60,235,140,70, "J6 Port C USB-C", ["'USB4 FAST' · PD sink: Pro", "Base: VBUS → detect only"], [("R",0.66,"VBUS","VBUS"),("R",0.9,"CC","CC1/CC2")], port_fs=8) s.block("PDA", 230,188,160,50, "TPS25750-A", ["Port A PD sink/source ctrl", "OVP 22 V + TVS"], [("L",0.3,"CC","CC")], port_fs=8, title_fs=11) s.block("PDC", 230,318,160,50, "TPS25750-C (Pro)", ["Port C PD sink ctrl", "PORTC_PD_PRESENT → EC"], [("L",0.3,"CC","CC")], port_fs=8, title_fs=11, dashed=True) s.block("MUX", 410,150,160,98, "VBUS priority mux (Pro)", ["TPS2121-class, Port A priority", "break-before-make, reverse block", "5–20 V ≤ 3.25 A (verify at 65 W)"], [("L",0.7,"A","A"),("L",0.9,"B","B"),("R",0.8,"OUT","OUT"),("B",0.5,"ST","")], port_fs=8, title_fs=11, dashed=True) s.block("CHG", 600,140,150,130, "BQ25792", ["buck-boost NVDC charger", "1–4S · 5 A charge · 7 A system", "input limit 3.3 A at 20 V", "2× 22 µF + TVS at VBUS_IN"], [("L",0.62,"VIN","VBUS_IN"),("L",0.86,"BAT","BAT"),("R",0.72,"VSYS","VSYS"),("B",0.3,"I2C",""),("B",0.7,"TS","")], port_fs=8) s.block("J12", 60,400,140,100, "J12 Battery pack", ["6-pin, harness W-02 ← PB J1", "see PU-W-202 / PU-W-204"], [("R",0.5,"PP","PACK+"),("R",0.62,"PM","PACK−"),("R",0.78,"SMB","SMBus"),("R",0.92,"NTC","NTC / PRES#")], port_fs=8) # CC lines (CTRL) for a,b in (("J4","PDA"),("J6","PDC")): (cx1,cy1),(cx2,cy2) = s.A(a,"CC"), s.A(b,"CC") s.wire("CTRL", [(cx1,cy1),(220,cy1),(220,cy2),(cx2,cy2)]) # VBUS A → mux A (P-01) ax,ay = s.A("J4","VBUS"); mx,my = s.A("MUX","A") s.wire("POWER", [(ax,ay),(400,ay),(400,my),(mx,my)], "VBUS 5–20 V ≤ 3.25 A used (100 W tolerated)", lid="P-01", seg=0, fs=8) s.junction("POWER", 400, ay) # Base bypass (REF) vx,vy = s.A("CHG","VIN") s.wire("REF", [(400,ay),(588,ay),(588,vy),(vx,vy)], "Base: 0 Ω bypass (no mux)", seg=0, fs=8, dy=-4, lfill="#555") s.junction("POWER", 588, vy) # VBUS C → mux B (P-02) bx,by = s.A("J6","VBUS"); mbx,mby = s.A("MUX","B") s.wire("POWER", [(bx,by),(400,by),(400,mby),(mbx,mby)], "VBUS 5–20 V (Pro) — Base: detect only", lid="P-02", seg=0, fs=8) # mux out → charger (P-03) ox,oy = s.A("MUX","OUT") s.wire("POWER", [(ox,oy),(588,oy),(588,vy)]); s.label(ox+4, oy+13, "P-03", 8, bold=True) # mux status tag stx,sty = s.A("MUX","ST"); s.line("ANNOTATION", stx, sty, stx, sty+14, "#333", LW["fine"]); s.tag(stx-40, sty+24, "VBUS_MUX_STAT → EC", "R", 8) # charger bottom tags ix,iy = s.A("CHG","I2C"); s.line("ANNOTATION", ix, iy, ix, iy+14, "#333", LW["fine"]); s.tag(ix-60, iy+24, "PD_I2C ↔ EC, TPS25750-A", "R", 8) tx,ty = s.A("CHG","TS"); s.line("ANNOTATION", tx, ty, tx, ty+14, "#333", LW["fine"]); s.tag(tx+10, ty+44, "TS ← pack NTC (J12, secondary)", "L", 8) # pack → BAT (P-04) px,py = s.A("J12","PP"); bcx,bcy = s.A("CHG","BAT") s.wire("POWER", [(px,py),(560,py),(560,bcy),(bcx,bcy)], "VBAT 5.6–8.4 V (2S) · 5 A charge / 7 A system · pack fuse 10 A", lid="P-04", seg=0, fs=8) s.junction("POWER", 560, py) # PACK− → one-point GND bond (W-20) nx,ny = s.A("J12","PM") s.wire("POWER", [(nx,ny),(440,ny),(440,ny+40)]) s.gnd(440, ny+40, chassis=False) s.label(330, ny+72, "W-20 one-point bond to MB GND near the charger (09 §6)", 8, fill=STYLE["BOND"]["stroke"]) # SMBus / NTC tags sx,sy = s.A("J12","SMB"); s.wire("BUS", [(sx,sy),(sx+22,sy)]); s.tag(sx+24, sy, "PACK_SMBUS ↔ EC (BQ40Z50-R2)", "R", 8) qx,qy = s.A("J12","NTC"); s.wire("CTRL", [(qx,qy),(qx+22,qy)]); s.tag(qx+24, qy, "NTC → BQ25792 TS · PRES# → EC", "R", 8) # ---------------- bucks ---------------- def buck(bid, y, title, sub, dashed=False): s.block(bid, 830,y,150,56, title, sub, [("L",0.4,"IN",""),("L",0.86,"EN","EN"),("R",0.5,"OUT","")], port_fs=8, title_fs=10.5, dashed=dashed) buck("B5", 113, "5.0 V SYS buck 6 A", ["TPS56637 (verify) · ≤ 3.1 A out"]) buck("BPB", 197, "5.0 V PORT B buck 3 A", ["TPS62933 class · EN on Port B attach"]) buck("BS", 260, "3.3 V SLOTS buck 4 A", ["LMR33640 · ≤ 3.85 A (6 A class Pro)"]) buck("BL", 449, "3.3 V LOGIC buck 4 A", ["LMR33640 · ≤ 3.1 A Pro peak"]) s.block("AON", 830,660,150,50, "3.3 V AON LDO", ["TPS7A16 100–150 mA · always on"], [("L",0.5,"IN",""),("R",0.5,"OUT","")], port_fs=8, title_fs=10.5) # VSYS bus vsx,vsy = s.A("CHG","VSYS") ys = [s.A(b,"IN")[1] for b in ("B5","BPB","BS","BL")] s.wire("POWER", [(vsx,vsy),(785,vsy),(785,ys[0])]) s.wire("POWER", [(785,ys[0]),(785,ys[-1])]) s.label(797, 440, "VSYS 6–8.4 V ≤ 7 A", 8.5, fill="#111", rotate=-90) s.label(772, 470, "VSYS bulk caps: 05 §10.2 vs 09 §5.1 — OI-6", 7.5, fill="#333", rotate=-90) for b,pid in zip(("B5","BPB","BS","BL"),("P-05","P-06","P-07","P-08")): x,y = s.A(b,"IN"); s.wire("POWER", [(785,y),(x,y)], pid, fs=8, dy=-3) if y != ys[0]: s.junction("POWER", 785, y) s.junction("POWER", 785, vsy) # VBAT → AON LDO (P-09) ax_,ay_ = s.A("AON","IN") s.wire("POWER", [(560,py),(560,ay_),(ax_,ay_)], "VBAT → AON LDO (05 §4); 09 §5.1 says VSYS — OI-5", lid="P-09", seg=1, fs=8, dy=-4) # ---------------- EC block + enables ---------------- s.block("EC", 600,540,190,84, "nRF5340 EC (3.3 V AON)", ["owns rail sequencing (05 §4)", "PMIC_EN → SoM · ASM2464_PWR_EN → load sw.", "CFEB…CFAST_PWR_EN → mezz 55–59", "PORTB_VBUS_EN / ILIM → TPS2596 Port B"], [("R",0.9,"EN",""),("L",0.9,"I2C","")], port_fs=8, title_fs=10.5) s.label(814, s.A("EC","EN")[1]+22, "EN / PG", 8, fill=STYLE["CTRL"]["stroke"]) ex,ey = s.A("EC","EN"); ens = [s.A(b,"EN")[1] for b in ("B5","BPB","BS","BL")] s.wire("CTRL", [(ex,ey),(808,ey),(808,ens[0])]) for b in ("B5","BPB","BS","BL"): x,y = s.A(b,"EN"); s.wire("CTRL", [(808,y),(x,y)]); s.junction("CTRL", 808, y) s.label(816, 440, "buck EN / PG (sequencing)", 8, fill=STYLE["CTRL"]["stroke"], rotate=-90) lx,ly = s.A("EC","I2C"); s.wire("BUS", [(lx,ly),(lx-20,ly)]); s.tag(lx-22, ly, "PD_I2C: TPS25750-A/-B/-C, BQ25792 · PACK_SMBUS: J12", "L", 8) # ---------------- consumers ---------------- CX, CW, CH = 1220, 230, 34 rows = [ # (rail, P, title, sub, dashed) ("B5", "P-11", "SoM VIN via J1/J2 (RK806 PMIC on SoM)", "5.0 V ±3 % · ≤ 1.6 A (8 W pk) · PMIC_EN ← EC", False), ("B5", "P-12", "Port A source eFuse 1.5 A → J4 VBUS", "5 V/1.5 A source role (PR_Swap phone top-up)", False), ("B5", "P-13", "OLED VCC boost 12 V → J10 (or in module)", "TPS61041 class · ~30 mA · display on only", False), ("BPB", "P-14", "TPS2596 eFuse → J5 Port B VBUS", "0.5 / 1.5 / 3 A (EC ILIM; 3 A only with PD, D13) · 3.3 A trip", False), ("BS", "P-15", "J3 mezz pins 44–51 (8 pins) → RB slot eFuses", "≥ 6 A total, 0.75 A/pin derated → RB block below", False), ("BS", "P-16", "eFuse 2.5 A → J9 M.2 NVMe 3.3 V (Pro)", "≤ 1.8 A · alt.: separate 3 A buck (EVT decision)", True), ("BL", "P-18", "ASM2812 switch I/O + 1.05 V local buck", "TPS62823 ≤ 15 mm from chip · ~1 A core", False), ("BL", "P-19", "RTL8126 5GbE I/O + 1.05 V local buck", "≤ 1.5 A core", False), ("BL", "P-20", "ASM3142 xHCI + 1.05 V local buck", "", False), ("BL", "P-21", "Load switch → ASM2464PD + 1.05 V + flash (Pro)", "ASM2464_PWR_EN ← EC · unpowered in standalone", True), ("BL", "P-22", "J8 M.2 Key-E MT7925 via LC π filter", "3.3 V · < 20 mVpp ripple · ≤ 0.75 A", False), ("BL", "P-23", "PI3DBS16412 · clk mux · latch · TPM · PD ctrls", "3.3 V small loads", False), ("BL", "P-24", "J3 mezz 52–53 → RB GL9755 / GL9750 / ASM1064", "3.3 V ~0.4 A (+ RB 1.2 V ASM1064 core)", False), ("BL", "P-25", "1.8 V buck 1 A → UHS-II (mezz 54), TPM, misc I/O", "0.6 A · 05 §5 lists a TLV75518 LDO instead — OI-7", False), ("AON", "P-10", "EC nRF5340 · Hall · RTC (MS621) · LED bar", "≤ 120 mA · LED bar ≤ 100 mA, else 5 V driver (OI-15)", False), ] ycs = [96 + i*42 for i in range(len(rows))] busx = {"B5":1010, "BS":1050, "BL":1070} # bus verticals for rail,bx_ in busx.items(): ys_ = [yc for (r,*_),yc in zip(rows,ycs) if r==rail] ox_,oy_ = s.A(rail,"OUT") s.wire("POWER", [(ox_,oy_),(bx_,oy_)]) s.wire("POWER", [(bx_,min(ys_+[oy_])),(bx_,max(ys_+[oy_]))]) s.junction("POWER", bx_, oy_) railtxt = {"B5":"5.0 V SYS","BS":"3.3 V SLOTS","BL":"3.3 V LOGIC"} s.label(1010-4, 90, "5.0 V SYS", 8, anchor="end", fill="#111") s.label(1050-4, 258, "3.3 V SLOTS", 8, anchor="end", fill="#111") s.label(1070-4, 342, "3.3 V LOGIC", 8, anchor="end", fill="#111") for (rail,pid,title,sub,dashed),yc in zip(rows,ycs): s.block("C"+pid, CX, yc-CH/2, CW, CH, title, [sub] if sub else None, [("L",0.5,"IN","")], title_fs=9, port_fs=8, dashed=dashed) if rail in busx: bx_ = busx[rail] s.wire("POWER", [(bx_,yc),(CX,yc)]) ys_ = [y for (r,*_),y in zip(rows,ycs) if r==rail] ox_,oy_ = s.A(rail,"OUT") if yc not in (min(ys_+[oy_]), max(ys_+[oy_])) or True: s.junction("POWER", bx_, yc) else: ox_,oy_ = s.A(rail,"OUT"); s.wire("POWER", [(ox_,oy_),(1100,oy_),(1100,yc),(CX,yc)]) s.label(1104, yc-5, pid, 8, fill="#111", bold=True) # fix consumer-block title/sub vertical placement (block() puts title at y+16, sub at y+30 → within 34 px block OK) # ---------------- RB slot power sub-block ---------------- RX, RY = 1180, 738 s.block("RB", RX, RY, 360, 236, "Reader daughterboard (RB) — slot power", ["From J3/J6 pins 44–51 (P-15) · EN = PWR_EN (pins 55–59) AND card-detect", "TPS2596 class: soft-start 1–2 ms · CFe B active discharge · FLT# → pin 60"], [("T",0.08,"IN","")], title_fs=10.5, fill="#f2f5fa") slots = [("CFe B J1", "2.5 A (09) / 2.0 A (05)"), ("CFe A J2", "1.5 A (09) / 1.2 A (05)"), ("CFast J5", "1.0 A (09) / 1.2 A (05)"), ("SD UHS-II J3", "0.8 A (09) / 0.5 A (05)"), ("microSD J4", "0.5 A (09) / 0.3 A (05)")] yy = RY+68 s.wire("POWER", [(RX+29,RY),(RX+29,yy-2)]) s.label(RX+34, RY-6, "P-17", 8, bold=True) for i,(name,lim) in enumerate(slots): yr = yy + i*32 s.rect("EQUIPMENT", RX+40, yr-11, 170, 24, "#fff", "#222", LW["secondary"], 2) s.text("EQUIPMENT", RX+125, yr-1, "eFuse " + name.split(" ")[0], 8.5, "middle", bold=True) s.text("EQUIPMENT", RX+125, yr+9, "limit " + lim, 7.5, "middle", "#333") s.rect("EQUIPMENT", RX+250, yr-11, 100, 24, "#fff", "#222", LW["secondary"], 2) s.text("EQUIPMENT", RX+300, yr+4, name, 8.5, "middle") s.wire("POWER", [(RX+29,yr),(RX+40,yr)]); s.junction("POWER", RX+29, yr) if i else None s.wire("POWER", [(RX+210,yr),(RX+250,yr)], "3.3 V", fs=7, dy=-2) s.wire("POWER", [(RX+29,yy),(RX+29,yy+4*32)]) s.label(RX+8, RY+220, "Current-limit conflict 09 §5.2 vs 05 §3.2/§4 — OI-2.", 7.5, fill="#9c1f1f") s.label(RX+8, RY+230, "Slot 3.3 V is applied only with a card present (09 §5.2).", 7.5, fill="#9c1f1f") # link P-15 consumer to RB block with a REF hint # ---------------- rail table ---------------- s.subheading(60, 748, "RAIL SUMMARY (09 §5.1, 05 §3.2)", 9.5) rail_rows = [ ["VBUS_IN 5–20 V", "Pro: TPS2121-class mux (A priority) · Base: Port A via 0 Ω", "≤ 3.25 A", "BQ25792 input"], ["VSYS 6–8.4 V", "BQ25792 NVDC output", "≤ 7–8 A", "all bucks, EC LDO (per 09)"], ["5.0 V SYS", "TPS56637 buck", "6 A (≤ 3.1 A used)", "SoM, Port A 1.5 A source, OLED boost"], ["5.0 V PORT B", "TPS62933 buck, ex-modem area", "3 A", "Port B VBUS via TPS2596 (EC ILIM)"], ["3.3 V SLOTS", "LMR33640 buck", "4 A (6 A class Pro)", "5 slot eFuses via mezz 44–51; NVMe eFuse (Pro)"], ["3.3 V LOGIC", "LMR33640 buck", "4 A (≤ 3.1 A Pro)", "ASM2812, RTL8126, Key-E, ASM3142, GL975x/ASM1064, PD ctrls, mux, TPM, ASM2464PD (Pro)"], ["1.8 V", "buck 1 A", "0.6 A", "UHS-II, TPM, misc I/O"], ["1.05 / 1.2 V", "point-of-load bucks TPS62823, one per chip", "≤ 1.5 A each", "ASM2812, RTL8126, ASM2464PD, ASM3142 cores"], ["3.3 V AON", "TPS7A16 LDO from VBAT (05) / VSYS (09)", "100–150 mA", "nRF5340, Hall, RTC, SMBus pull-ups"], ] s.table(60, 754, [90, 200, 95, 235], rail_rows, ["Rail", "Source", "Rating", "Consumers"], 7.6, pad=3) # ---------------- notes ---------------- notes = [ "Sequencing (EC-controlled, 05 §4): 3.3 V AON always on → LOGIC → SLOTS (eFuses off) → 5.0 V SYS (SoM boots) → 5.0 V PORT B only on Port B attach (Rp set before VBUS) → slot eFuses as cards are detected. Power-down reverses; slot eFuses drop after unmount or the EC hard-cut timer.", "PD attach (Pro, either port): Port A always wins at the mux; hand-over is break-before-make and the BQ25792 supplement mode rides the gap from the battery (no reset, VSYS droop ≤ 3–5 %). Input-current limit is re-programmed before the new input is made (05 §8).", "Every rail's return is board GND; the battery negative is bonded to board GND at one point near the charger (W-20). Chassis bonds are on PU-W-101.", "OI-2 slot eFuse limits differ between 09 §5.2 and 05 §3.2/§4 (both shown). OI-5 AON LDO source: VBAT (05 §4) vs VSYS (09 §5.1). OI-6 VSYS bulk capacitance differs (05 §10.2 vs 09 §5.1). OI-7 1.8 V: buck (09) vs LDO (05). OI-15 LED-bar supply: not on the mezzanine allocation.", "Base SKU: TPS25750-C, the VBUS mux, the ASM2464PD load-switch path and the NVMe eFuse load are absent; Port A VBUS feeds the charger through a 0 Ω bypass (09 §1.1). All ratings marked (verify) in the source documents remain to be confirmed against datasheets before EVT schematic release.", ] s.notes(700, 748, 460, "Notes", notes, 7.8) s.titleblock() return s.write()