wiring/src/w101.py
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from sheet import Sheet, LWimport model def draw(): s = Sheet("101", model.SHEETS[1][1]) x0,y0,x1,y1 = s.frame s.heading(x0+20, y0+22, "SYSTEM INTERCONNECT — boards, modules, harnesses, chassis bonds and external ports (logical, NTS)", 12) # ---------------- reader daughterboard (top) ---------------- RBX, RBY, RBW, RBH = 430, 74, 690, 90 s.block("RB", RBX, RBY, RBW, RBH, "RB — Reader daughterboard (8L, 172 × 38 mm, reader band)", ["Top edge, left→right: J5 CFast 2.0 | J1 CFexpress B | J2 CFexpress A | J3 SD UHS-II | J4 microSD", "GL9755 · GL9750 · ASM1064 · 5× eFuse (TPS2596 class) · card-detect ×5 · Hall sensor (baseline, OI-4) · RB EEPROM"], [("B", 60, "J6", "J6 mezzanine (ADF6, female)"), ("R", 47, "J7", "J7 LED bar"), ("R", 80, "GND", "GND (rail + cage pins)")]) # ---------------- main board (centre) ---------------- MBX, MBY, MBW, MBH = 430, 250, 690, 470 s.block("MB", MBX, MBY, MBW, MBH, "MB — Main board (10L hybrid, 165 × 80 mm)", None, [("T", 60, "J3", "J3 mezzanine (ADM6, male)"), ("L", 50, "J10", "J10 OLED FPC 30-pin"), ("L", 110, "J11", "J11 button flex 6-pin"), ("L", 250, "J12", "J12 battery pack 6-pin"), ("L", 273, "GNDP", "GND — pack − one-point bond"), ("L", 340, "THSW", "TP-THSW thermal-switch leads (TBD)"), ("L", 400, "J17", "J17 fan header (reserved)"), ("R", 71, "J8", "J8 M.2 Key-E 2230 — Wi-Fi"), ("R", 175, "J9", "J9 M.2 M-key 2280 — NVMe (Pro)"), ("R", 414, "GND", "GND — 8 screw bosses"), ("R", 454, "SH", "J4–J7 shells / RJ45 frame"), ("B", 70, "J4", "J4 Port A"), ("B", 190, "J5", "J5 Port B"), ("B", 310, "J6", "J6 Port C (Pro)"), ("B", 470, "J7", "J7 RJ45 5GBASE-T")]) s.label(820, 290, "ASM2812 switch · PI3DBS16412 + HCSL clock mux · ASM2464PD (Pro) · ASM3142 · RTL8126 + magnetics", 8.5, "middle", "#333") s.label(820, 302, "TPS25750 ×3 · TPS2121-class VBUS mux (Pro) · BQ25792 · bucks · TPM SLB9672 · nRF5340 EC + BLE chip antenna", 8.5, "middle", "#333") s.label(MBX+9, 690, "J13 SoC UART · J14 EC SWD (Tag-Connect) — debug, unpopulated at PVT", 8, "start", "#333") s.label(MBX+MBW-9, 540, "J15 / J16 spare PCIe Gen2 ×1 test headers (unpop.)", 8, "end", "#333") # SoM inside MB s.block("SOM", 600, 470, 260, 150, "SOM — RK3588(J) compute module", ["Firefly Core-3588J (v0.2 default) / Forlinx FET3588-C /", "board-down RK3588J — decided at PoC exit (D12)", "pcie3x4, pcie3x2, 3× Gen2, USB3 OTG0/1, USB2 ×2, SPI TPM,", "UART / I²C / GPIO to EC, 5.0 V SYS in"], [("L", 10, "B2B", "")], fill="#efefef") s.wire("MECH", [(600,480),(560,480)]) s.label(556, 484, "W-10 mated on J1 / J2 (B2B)", 8.5, "end", "#444") # cross-reference tags inside MB for i,(t) in enumerate(["PU-W-102 power", "PU-W-103 EC signals", "PU-W-104 CFe B path"]): s.tag(600+i*98, 652, t, "R", 8) # ---------------- W-01 mezzanine ---------------- s.wire("HS", [s.A("RB","J6"), s.A("MB","J3")]) s.label(498, 198, "W-01 Samtec ADM6 / ADF6 80-pin, direct mate, stack 5–8 mm (height TBD)", 8.5, "start", "#1f4e9c") s.label(498, 210, "CFe B Gen3/Gen4 ×2 + REFCLK + sidebands · CFe A ×1 · 3× Gen3 ×1 · 3.3 V slots / logic · 1.8 V · EC signals", 8, "start", "#333") s.tag(498, 226, "PU-W-201 pin allocation", "R", 8) # ---------------- left column ---------------- LX, LW_ = 60, 240 s.block("OLED", LX, 280, LW_, 40, "OLED — 2.42\" 128 × 64, SSD1309", None, [("R", 0.5, "FPC", "")], title_fs=10) s.wire("BUS", [s.A("OLED","FPC"), s.A("MB","J10")]) s.label(302, 293, "W-03 OLED FPC 30-pin", 8.5, "start", "#8a4b00"); s.label(302, 312, "SPI · VDD 3.3 · VCC 12 V", 8, "start", "#333") s.block("BTNFLX", LX, 340, LW_, 40, "BTNFLX — button flex (front frame)", None, [("R", 0.5, "FPC", "")], title_fs=10) s.wire("CTRL", [s.A("BTNFLX","FPC"), s.A("MB","J11")]) s.label(302, 353, "W-04 flex 6-pin (proposed)", 8.5, "start", "#1b7a3a"); s.label(302, 372, "BTN · ring LED · 3.3 V AON", 8, "start", "#333") s.block("PACK", LX, 410, LW_, 140, "PACK — battery pack 2S2P 21700, 72 Wh", ["certified sub-assembly, behind screw-down door"], [], fill="#fbfbfb") s.block("PB", LX+20, 455, 200, 82, "PB — pack PCB (2L)", ["BQ40Z50-R2 · BQ294xx · 10 A fuse · 2× NTC"], [("R", 45, "J1", "J1"), ("R", 68, "PN", "PACK−")], title_fs=10) s.wire("POWER", [s.A("PB","J1"), s.A("MB","J12")]) s.label(302, 493, "W-02 6-way pack harness", 8.5, "start", "#111"); s.label(302, 511, "PACK± · SMBus · NTC · PRES#", 8, "start", "#333") s.wire("BOND", [s.A("PB","PN"), s.A("MB","GNDP")]) s.label(302, 536, "W-20 pack − bond, one point", 8, "start", "#4c7c1c") s.tag(LX, 559, "PU-W-202 pack · PU-W-204 J12 pinout", "R", 8) s.block("THSW", LX, 570, LW_, 40, "THSW — mechanical thermal switch", ["chassis inner wall, location TBD (OI-1)"], [("R", 0.5, "L", "")], title_fs=10, dashed=True) s.wire("CTRL", [s.A("THSW","L"), s.A("MB","THSW")]) s.label(302, 583, "W-08 2 leads, termination TBD", 8.5, "start", "#1b7a3a"); s.label(302, 602, "THERM_ALERT (OI-1)", 8, "start", "#333") s.block("FAN", LX, 630, LW_, 40, "FAN — tunnel fan (reserved envelope)", ["not fitted; decision at EVT exit (D5)"], [("R", 0.5, "L", "")], title_fs=10, dashed=True) s.wire("REF", [s.A("FAN","L"), s.A("MB","J17")]) s.label(302, 643, "W-09 3-pin, unpopulated", 8.5, "start", "#777") # ---------------- right column ---------------- RX, RW = 1230, 210 s.block("LEDBAR", RX, 95, RW, 45, "LEDBAR — 5-segment RGB bar", ["front top edge, over the slot row"], [("L", 22, "IN", "")], title_fs=10) s.wire("CTRL", [s.A("RB","J7"), s.A("LEDBAR","IN")]) s.label(1175, 108, "W-07 LED_DATA", 8.5, "middle", "#1b7a3a"); s.label(1175, 130, "on-RB LEDs / FPC alt. (TBD)", 7.8, "middle", "#333") s.block("ANTW0", RX, 175, 100, 42, "ANTW0", ["Wi-Fi flex, X 12–52"], [("B", 0.5, "PIG", "")], title_fs=10) s.block("ANTW1", RX+115, 175, 95, 42, "ANTW1", ["Wi-Fi flex, X 130–170"], [("B", 0.5, "PIG", "")], title_fs=10) s.block("WIFI", RX, 290, RW, 90, "WIFI — M.2 Key-E 2230, MT7925", ["Wi-Fi 7 2×2; pcie2x1l1; BT held in reset", "2× MHF4 (I-PEX 20449) on the module"], [("T", 50, "ANT0", ""), ("T", 162, "ANT1", ""), ("L", 0.4, "M2", "")], title_fs=10) s.wire("RF", [s.A("WIFI","ANT0"), s.A("ANTW0","PIG")]); s.wire("RF", [s.A("WIFI","ANT1"), s.A("ANTW1","PIG")]) s.label(1284, 243, "W-05 MHF4 coax", 8, "start", "#9c1f1f"); s.label(1284, 254, "≈140–150 mm (est.)", 7.8, "start", "#333") s.label(1396, 243, "W-06 MHF4", 8, "start", "#9c1f1f"); s.label(1396, 254, "≈60 mm (est.)", 7.8, "start", "#333") s.label(1284, 286, "ANT0", 7.8, "start", "#333"); s.label(1396, 286, "ANT1", 7.8, "start", "#333") s.wire("MECH", [s.A("MB","J8"), s.A("WIFI","M2")]) s.label(1175, 314, "W-11 mated in J8", 8.5, "middle", "#444") s.block("NVME", RX, 400, RW, 50, "NVME — M.2 M-key 2280 SSD (Pro)", ["socket J9 present, empty on Base"], [("L", 0.5, "M2", "")], title_fs=10, dashed=True) s.wire("MECH", [s.A("MB","J9"), s.A("NVME","M2")]) s.label(1175, 418, "W-12 mated in J9 (Pro)", 8.5, "middle", "#444") s.block("CHASSIS", RX, 640, RW, 80, "CHASSIS — Mg AZ91D die-cast", ["ground reference; masked bare conversion-", "coated lands; Zn-Ni / Al fasteners only (D4)"], [("L", 24, "B17", ""), ("L", 64, "B19", ""), ("R", 24, "B18", "")], title_fs=10) s.gnd(RX+RW-30, 690, chassis=True) s.wire("BOND", [s.A("MB","GND"), s.A("CHASSIS","B17")]); s.label(1175, 657, "W-17 8 bosses", 8, "middle", "#4c7c1c") s.wire("BOND", [s.A("MB","SH"), s.A("CHASSIS","B19")]); s.label(1175, 697, "W-19 brackets / frame", 8, "middle", "#4c7c1c") gx, gy = s.A("RB","GND") s.wire("BOND", [(gx,gy), (1500,gy), (1500,664), s.A("CHASSIS","B18")]) s.label(1513, 400, "W-18 RB GND via mounting rail + cage pins", 8, "start", "#4c7c1c", rotate=-90) # ---------------- external ports (bottom) ---------------- EY = 790 ext = [("EXT-A", 500, "EXT-A — Port A host", ["iPhone · Mac · PC · charger", "PD ≤ 100 W · USB3 Gen1"], False, "W-13", "USB-C cable"), ("EXT-B", 620, "EXT-B — Port B device", ["SSD · tethered phone ·", "USB cellular adapter"], False, "W-14", "USB-C cable"), ("EXT-C", 740, "EXT-C — Port C host (Pro)", ["USB4 host / PD source", "blanked on Base"], True, "W-15", "USB-C (USB4)"), ("EXT-LAN", 900, "EXT-LAN — network", ["5GBASE-T, hinged door", "IP54 closed"], False, "W-16", "Cat 6A patch")] for bid, px, title, sub, dashed, wid, med in ext: s.block(bid, px-60, EY, 120, 52, title, sub, [("T", 0.5, "P", "")], title_fs=9, dashed=dashed) port = {"EXT-A":"J4","EXT-B":"J5","EXT-C":"J6","EXT-LAN":"J7"}[bid] s.wire("HS", [s.A("MB",port), s.A(bid,"P")]) s.label(px+5, 750, wid, 8.5, "start", "#1f4e9c"); s.label(px+5, 761, med, 7.8, "start", "#333") s.tag(1000, 816, "PU-W-203 port and module wiring", "R", 8) s.tag(1000, 840, "PU-W-204 peripheral pinouts", "R", 8) # ---------------- notes ---------------- notes = [ "Baseline ADR v0.3 (2026-09-27). Logical interconnect only: block positions and line lengths carry no physical meaning; no cable length is measured.", "Dashed outlines = Pro-only population, reserved or TBD. Pro adds the NVMe in J9, Port C data (ASM2464PD) and Port C PD sink (TPS25750-C + TPS2121-class VBUS mux) on the same PCB; J6 receptacle is fitted on both SKUs and blanked on Base.", "Harness lengths (W-02, W-05, W-06) are estimates from the docs/08 layout. RB-to-MB mezzanine stack height and ADM6/ADF6 variant are set when docs/08 fixes the spacing (09 §13).", "Conflicts carried to PU-W-000: OI-3 pack connector family / current per pin; OI-4 Hall sensor on RB (mezzanine pin 66) vs on the J11 flex; OI-10 SoM connector count (2 vs 3 B2B). Not applicable if board-down is chosen (D12).", "W-08 thermal switch: rating (48 °C vs 60 °C class, OI-1), location and interrupted circuit are fixed at EVT schematic release. J17 fan header stays unpopulated until the EVT-exit fan gate (D5).", "Chassis bonds W-17…W-20: 8 MB screw bosses on exposed L1 GND rings, RB rail + cage pins, connector brackets / RJ45 frame, pack − at one point near the charger (09 §6). Bare conversion-coated Mg lands; never stainless into Mg (D4).", "Detail sheets: PU-W-102 power, PU-W-103 EC signals, PU-W-104 CFe B mode-switch path, PU-W-201 mezzanine, PU-W-202 pack, PU-W-203 ports and modules, PU-W-204 pinouts, PU-W-301 schedule.", ] s.notes(LX, 700, 340, "Notes", notes, 8) s.titleblock() return s.write()