wiring/src/w000.py
3.7 KB · 48 lines · python · Download from the repository page
from sheet import Sheet, LEGEND_ORDER, LEGEND_TEXT, STYLE, LWimport modeldef draw(): s = Sheet("000", model.SHEETS[0][1]) x0,y0,x1,y1 = s.frame s.heading(x0+20, y0+40, f"{model.PROJECT}", 22) s.heading(x0+20, y0+70, f"{model.SET_TITLE} — Rev {model.REV} ({model.BASELINE}), {model.DATE}", 15) s.label(x0+20, y0+92, f"Status: {model.STATUS}. Logical wiring and connection diagrams — not to scale; no physical routing or cable lengths are implied unless a length is stated with its basis.", 10, fill="#9c1f1f") # index s.subheading(x0+20, y0+125, "DRAWING INDEX") rows = [[model.sheet_no(n), t, "A", "NTS"] for n,t in model.SHEETS] yb = s.table(x0+20, y0+132, [90, 520, 40, 60], rows, ["Sheet", "Title", "Rev", "Scale"], 9) # conventions s.subheading(x0+20, yb+28, "CONVENTIONS") conv = [ "Sheet size A3 landscape (420 × 297 mm), zones 1–8 across / A–F down. Lineweights: 0.50 mm borders and block outlines, 0.35 mm primary connections, 0.25 mm secondary, 0.18 mm leaders and dimensions.", "Connection classes are shown by colour AND line type (legend, right) so monochrome prints remain readable. Junction dots mark intentional joins; crossings without a dot are not connected.", "Equipment IDs: MB main board, RB reader daughterboard, PB pack PCB, SOM compute module, WIFI / NVME M.2 modules, OLED, BTNFLX button flex, ANTW0/1 Wi-Fi antennas, THSW thermal switch, CHASSIS. Connector refs (J1…) are those of docs/09 §9.", "Connection IDs: W-nn off-board (cables, flexes, mated modules, bonds — schedule on PU-W-301 and PU_Connection-Schedule_Rev-A.csv); P-nn on-board power links (PU-W-102). Signal names follow docs/02 §8 and docs/09 §8.", "Evidence classes in the schedule: Verified (stated in docs/00–13 or a public standard), Derived, Assumed (drafting proposal — confirm at schematic capture), TBD. Nothing here is a manufacturer pinout unless the standard is named.", "Base / Pro SKU: items populated on the Pro SKU only (ASM2464PD, Port C PD controller TPS25750-C, TPS2121-class VBUS mux, NVMe) are marked 'Pro'; the PCB is common.", "Layers in the SVG source: L-BORDER, L-TITLE, L-REFERENCE, L-EQUIPMENT, L-CONN-POWER/HS/CTRL/BUS/RF/BOND/REF/MECH, L-ANNOTATION, L-REVISION.", ] yb2 = s.notes(x0+20, yb+36, 710, "General notes", conv, 8.5) # legend large lx = x0+760 s.subheading(lx, y0+125, "LEGEND") ly = y0+140 for c in LEGEND_ORDER: st = STYLE[c] s.line("ANNOTATION", lx, ly, lx+70, ly, st["stroke"], st["sw"], st["dash"]) s.label(lx+80, ly+4, f"{c}: {LEGEND_TEXT[c]}", 9.5) ly += 18 # symbols s.gnd(lx+20, ly+6, chassis=True); s.label(lx+80, ly+16, "Chassis ground (magnesium chassis, masked conversion-coated land)", 9.5) ly += 34; s.gnd(lx+20, ly+6, chassis=False); s.label(lx+80, ly+16, "Signal / board ground", 9.5) ly += 34; s.junction("HS", lx+35, ly+6); s.label(lx+80, ly+10, "Junction (intentional connection)", 9.5) ly += 24; s.tag(lx+10, ly+6, "PU-W-102 / P-05", "R"); s.label(lx+80+60, ly+10, "Off-sheet reference: sheet / connection ID", 9.5) ly += 24; s.block("legB", lx, ly, 70, 44, "BLOCK", None, [("L",0.72,"p","PORT")], port_fs=8); s.label(lx+80, ly+26, "Equipment block with port stub and port label", 9.5) ly += 56; s.rect("ANNOTATION", lx, ly, 70, 22, "#f7f7f7", "#222", LW["primary"], 3, 'stroke-dasharray="6 3"'); s.label(lx+80, ly+15, "Dashed outline: Pro-only population, reserved or TBD item", 9.5) # open items ly += 44 s.subheading(lx, ly, "OPEN ITEMS AND SOURCE-DOCUMENT CONFLICTS FOUND WHILE DRAFTING (details: PU_Validation_Rev-A.md)") rows = [[o[0], o[1], o[2], o[3]] for o in model.OPEN_ITEMS] s.table(lx, ly+8, [40, 150, 470, 70], rows, ["ID", "Item", "Conflict / gap", "Docs"], 7.8) s.titleblock(legend=False) return s.write()