wiring/preview/PU-W-000.meta.json
18 KB · 1 lines · json · Download from the repository page
{"number": "000", "title": "Cover, index, legend, general notes, open items", "texts": [[131.8025, 26.8, 136.57250000000002, 35.8, "1", "BORDER"], [131.8025, 1089.8, 136.57250000000002, 1098.8, "1", "BORDER"], [320.1775, 26.8, 324.9475, 35.8, "2", "BORDER"], [320.1775, 1089.8, 324.9475, 1098.8, "2", "BORDER"], [508.5525, 26.8, 513.3225, 35.8, "3", "BORDER"], [508.5525, 1089.8, 513.3225, 1098.8, "3", "BORDER"], [696.9275, 26.8, 701.6975, 35.8, "4", "BORDER"], [696.9275, 1089.8, 701.6975, 1098.8, "4", "BORDER"], [885.3025, 26.8, 890.0725, 35.8, "5", "BORDER"], [885.3025, 1089.8, 890.0725, 1098.8, "5", "BORDER"], [1073.6775, 26.8, 1078.4475, 35.8, "6", "BORDER"], [1073.6775, 1089.8, 1078.4475, 1098.8, "6", "BORDER"], [1262.0525, 26.8, 1266.8225, 35.8, "7", "BORDER"], [1262.0525, 1089.8, 1266.8225, 1098.8, "7", "BORDER"], [1450.4275, 26.8, 1455.1975, 35.8, "8", "BORDER"], [1450.4275, 1089.8, 1455.1975, 1098.8, "8", "BORDER"], [27.615, 122.71666666666668, 32.385, 131.7166666666667, "A", "BORDER"], [1554.615, 122.71666666666668, 1559.385, 131.7166666666667, "A", "BORDER"], [27.615, 296.55, 32.385, 305.55, "B", "BORDER"], [1554.615, 296.55, 1559.385, 305.55, "B", "BORDER"], [27.615, 470.3833333333333, 32.385, 479.3833333333333, "C", "BORDER"], [1554.615, 470.3833333333333, 1559.385, 479.3833333333333, "C", "BORDER"], [27.615, 644.2166666666666, 32.385, 653.2166666666666, "D", "BORDER"], [1554.615, 644.2166666666666, 1559.385, 653.2166666666666, "D", "BORDER"], [27.615, 818.05, 32.385, 827.05, "E", "BORDER"], [1554.615, 818.05, 1559.385, 827.05, "E", "BORDER"], [27.615, 991.8833333333333, 32.385, 1000.8833333333333, "F", "BORDER"], [1554.615, 991.8833333333333, 1559.385, 1000.8833333333333, "F", "BORDER"], [60, 62.4, 444.78000000000003, 84.4, "PoppyUp \u2014 Phase 1 Hardware Design", "ANNOTATION"], [60, 98.0, 568.8, 113.0, "Wiring & Interconnect Diagram Set \u2014 Rev A (ADR v0.3), 2026-09-27", "ANNOTATION"], [60, 124.0, 976.9000000000001, 134.0, "Status: DRAFT \u2014 FOR REVIEW. Logical wiring and connection diagrams \u2014 not to scale; no physical routing or cable lengths are implied unless a length is stated with its basis.", "ANNOTATION"], [60, 156.6, 132.345, 167.1, "DRAWING INDEX", "ANNOTATION"], [64, 177.8, 87.85, 186.8, "Sheet", "ANNOTATION"], [154, 177.8, 177.85, 186.8, "Title", "ANNOTATION"], [674, 177.8, 688.31, 186.8, "Rev", "ANNOTATION"], [714, 177.8, 737.85, 186.8, "Scale", "ANNOTATION"], [64, 197.05, 102.16, 206.05, "PU-W-000", "ANNOTATION"], [154, 197.05, 378.19000000000005, 206.05, "Cover, index, legend, general notes, open items", "ANNOTATION"], [674, 197.05, 678.77, 206.05, "A", "ANNOTATION"], [714, 197.05, 728.31, 206.05, "NTS", "ANNOTATION"], [64, 216.3, 102.16, 225.3, "PU-W-101", "ANNOTATION"], [154, 216.3, 473.59000000000003, 225.3, "System interconnect \u2014 boards, modules, harnesses and external ports", "ANNOTATION"], [674, 216.3, 678.77, 225.3, "A", "ANNOTATION"], [714, 216.3, 728.31, 225.3, "NTS", "ANNOTATION"], [64, 235.55, 102.16, 244.55, "PU-W-102", "ANNOTATION"], [154, 235.55, 273.25, 244.55, "Power distribution wiring", "ANNOTATION"], [674, 235.55, 678.77, 244.55, "A", "ANNOTATION"], [714, 235.55, 728.31, 244.55, "NTS", "ANNOTATION"], [64, 254.8, 102.16, 263.8, "PU-W-103", "ANNOTATION"], [154, 254.8, 368.65000000000003, 263.8, "Embedded-controller control and sensor wiring", "ANNOTATION"], [674, 254.8, 678.77, 263.8, "A", "ANNOTATION"], [714, 254.8, 728.31, 263.8, "NTS", "ANNOTATION"], [64, 274.05, 102.16, 283.05, "PU-W-104", "ANNOTATION"], [154, 274.05, 506.98, 283.05, "CFexpress B mode-switch path \u2014 lane mux, clock mux, interlock, USB4 bridge", "ANNOTATION"], [674, 274.05, 678.77, 283.05, "A", "ANNOTATION"], [714, 274.05, 728.31, 283.05, "NTS", "ANNOTATION"], [64, 293.3, 102.16, 302.3, "PU-W-201", "ANNOTATION"], [154, 293.3, 368.65000000000003, 302.3, "Mezzanine J3 / J6 \u2014 80-pin connection diagram", "ANNOTATION"], [674, 293.3, 678.77, 302.3, "A", "ANNOTATION"], [714, 293.3, 728.31, 302.3, "NTS", "ANNOTATION"], [64, 312.55, 102.16, 321.55, "PU-W-202", "ANNOTATION"], [154, 312.55, 306.64, 321.55, "Battery pack sub-assembly wiring", "ANNOTATION"], [674, 312.55, 678.77, 321.55, "A", "ANNOTATION"], [714, 312.55, 728.31, 321.55, "NTS", "ANNOTATION"], [64, 331.8, 102.16, 340.8, "PU-W-203", "ANNOTATION"], [154, 331.8, 373.42, 340.8, "External ports and M.2 module connector wiring", "ANNOTATION"], [674, 331.8, 678.77, 340.8, "A", "ANNOTATION"], [714, 331.8, 728.31, 340.8, "NTS", "ANNOTATION"], [64, 351.05, 102.16, 360.05, "PU-W-204", "ANNOTATION"], [154, 351.05, 545.1400000000001, 360.05, "Peripheral connector pinouts \u2014 OLED, button flex, pack, debug, fan, thermal switch", "ANNOTATION"], [674, 351.05, 678.77, 360.05, "A", "ANNOTATION"], [714, 351.05, 728.31, 360.05, "NTS", "ANNOTATION"], [64, 370.3, 102.16, 379.3, "PU-W-301", "ANNOTATION"], [154, 370.3, 244.63, 379.3, "Connection schedule", "ANNOTATION"], [674, 370.3, 678.77, 379.3, "A", "ANNOTATION"], [714, 370.3, 728.31, 379.3, "NTS", "ANNOTATION"], [60, 403.35, 121.215, 413.85, "CONVENTIONS", "ANNOTATION"], [68, 427.15, 133.45499999999998, 436.65, "General notes", "ANNOTATION"], [68, 445.78999999999996, 761.77, 454.28999999999996, "1. Sheet size A3 landscape (420 \u00d7 297 mm), zones 1\u20138 across / A\u2013F down. Lineweights: 0.50 mm borders and block outlines, 0.35 mm primary connections, 0.25", "ANNOTATION"], [80, 456.84, 282.725, 465.34, "mm secondary, 0.18 mm leaders and dimensions.", "ANNOTATION"], [68, 467.89, 730.235, 476.39, "2. Connection classes are shown by colour AND line type (legend, right) so monochrome prints remain readable. Junction dots mark intentional joins;", "ANNOTATION"], [80, 478.94, 269.21000000000004, 487.44, "crossings without a dot are not connected.", "ANNOTATION"], [68, 489.99, 739.245, 498.49, "3. Equipment IDs: MB main board, RB reader daughterboard, PB pack PCB, SOM compute module, WIFI / NVME M.2 modules, OLED, BTNFLX button flex, ANTW0/1", "ANNOTATION"], [80, 501.04, 489.955, 509.54, "Wi-Fi antennas, THSW thermal switch, CHASSIS. Connector refs (J1\u2026) are those of docs/09 \u00a79.", "ANNOTATION"], [68, 512.0900000000001, 757.265, 520.5900000000001, "4. Connection IDs: W-nn off-board (cables, flexes, mated modules, bonds \u2014 schedule on PU-W-301 and PU_Connection-Schedule_Rev-A.csv); P-nn on-board power", "ANNOTATION"], [80, 523.1400000000001, 368.32, 531.6400000000001, "links (PU-W-102). Signal names follow docs/02 \u00a78 and docs/09 \u00a78.", "ANNOTATION"], [68, 534.19, 739.245, 542.69, "5. Evidence classes in the schedule: Verified (stated in docs/00\u201313 or a public standard), Derived, Assumed (drafting proposal \u2014 confirm at schematic", "ANNOTATION"], [80, 545.24, 449.40999999999997, 553.74, "capture), TBD. Nothing here is a manufacturer pinout unless the standard is named.", "ANNOTATION"], [68, 556.29, 748.255, 564.79, "6. Base / Pro SKU: items populated on the Pro SKU only (ASM2464PD, Port C PD controller TPS25750-C, TPS2121-class VBUS mux, NVMe) are marked 'Pro'; the", "ANNOTATION"], [80, 567.3399999999999, 143.07, 575.8399999999999, "PCB is common.", "ANNOTATION"], [68, 578.3899999999999, 707.71, 586.8899999999999, "7. Layers in the SVG source: L-BORDER, L-TITLE, L-REFERENCE, L-EQUIPMENT, L-CONN-POWER/HS/CTRL/BUS/RF/BOND/REF/MECH, L-ANNOTATION, L-REVISION.", "ANNOTATION"], [800, 156.6, 833.39, 167.1, "LEGEND", "ANNOTATION"], [880, 176.4, 1071.33, 185.9, "POWER: Power (VBUS, VBAT, VSYS, rails)", "ANNOTATION"], [880, 194.4, 1091.47, 203.9, "HS: High-speed data (PCIe, USB, USB4, MDI)", "ANNOTATION"], [880, 212.4, 1126.715, 221.9, "CTRL: Control / discrete (GPIO, enables, detects)", "ANNOTATION"], [880, 230.4, 1076.365, 239.9, "BUS: Serial bus (I\u00b2C, SMBus, SPI, UART)", "ANNOTATION"], [880, 248.4, 970.63, 257.9, "RF: RF coax (MHF4)", "ANNOTATION"], [880, 266.4, 1015.9449999999999, 275.9, "BOND: Chassis / ground bond", "ANNOTATION"], [880, 284.4, 1086.435, 293.9, "REF: Reserved, alternative or depopulated", "ANNOTATION"], [880, 302.4, 1111.6100000000001, 311.9, "MECH: Direct mate (module in socket, no cable)", "ANNOTATION"], [880, 332.4, 1207.275, 341.9, "Chassis ground (magnesium chassis, masked conversion-coated land)", "ANNOTATION"], [880, 366.4, 985.735, 375.9, "Signal / board ground", "ANNOTATION"], [880, 394.4, 1046.155, 403.9, "Junction (intentional connection)", "ANNOTATION"], [814, 418.2, 881.575, 426.7, "PU-W-102 / P-05", "ANNOTATION"], [940, 418.4, 1151.47, 427.9, "Off-sheet reference: sheet / connection ID", "ANNOTATION"], [819.1, 446.4, 850.9, 458.4, "BLOCK", "EQUIPMENT"], [809, 468.28000000000003, 825.96, 476.28000000000003, "PORT", "EQUIPMENT"], [880, 458.4, 1106.575, 467.9, "Equipment block with port stub and port label", "ANNOTATION"], [880, 503.4, 1166.995, 512.9, "Dashed outline: Pro-only population, reserved or TBD item", "ANNOTATION"], [800, 531.6, 1328.6750000000002, 542.1, "OPEN ITEMS AND SOURCE-DOCUMENT CONFLICTS FOUND WHILE DRAFTING (details: PU_Validation_Rev-A.md)", "ANNOTATION"], [804, 553.56, 812.268, 561.3599999999999, "ID", "ANNOTATION"], [844, 553.56, 860.5360000000001, 561.3599999999999, "Item", "ANNOTATION"], [994, 553.56, 1051.876, 561.3599999999999, "Conflict / gap", "ANNOTATION"], [1464, 553.56, 1480.536, 561.3599999999999, "Docs", "ANNOTATION"], [804, 571.31, 820.5360000000001, 579.1099999999999, "OI-1", "ANNOTATION"], [844, 571.31, 930.814, 579.1099999999999, "Thermal switch rating", "ANNOTATION"], [994, 571.31, 1452.874, 579.1099999999999, "48 \u00b0C in 02 \u00a78 / 06 \u00a77.2 / 09 \u00a77 vs '60 \u00b0C class, re-rated from 48 \u00b0C' in ADR 00 \u00a73.5; location and interrupted", "ANNOTATION"], [994, 581.06, 1076.68, 588.8599999999999, "circuit unspecified.", "ANNOTATION"], [1464, 571.31, 1521.876, 579.1099999999999, "00, 02, 06, 09", "ANNOTATION"], [804, 598.81, 820.5360000000001, 606.6099999999999, "OI-2", "ANNOTATION"], [844, 598.81, 947.35, 606.6099999999999, "Slot eFuse current limits", "ANNOTATION"], [994, 598.81, 1440.472, 606.6099999999999, "09 \u00a75.2: CFe B 2.5 / CFe A 1.5 / CFast 1.0 / SD 0.8 / \u00b5SD 0.5 A. 05 \u00a73.2, \u00a74: 2.0 / 1.2 / 1.2 / 0.5 / 0.3 A.", "ANNOTATION"], [1464, 598.81, 1488.804, 606.6099999999999, "05, 09", "ANNOTATION"], [804, 616.56, 820.5360000000001, 624.3599999999999, "OI-3", "ANNOTATION"], [844, 616.56, 980.422, 624.3599999999999, "Pack connector family and current", "ANNOTATION"], [844, 626.31, 872.938, 634.1099999999999, "per pin", "ANNOTATION"], [994, 616.56, 1436.338, 624.3599999999999, "6-pin JST GH/XA (09) vs Molex Micro-Fit / JST GH (05); one pin each for PACK+/\u2212 must carry 5 A charge / 7 A", "ANNOTATION"], [994, 626.31, 1332.988, 634.1099999999999, "system peaks; pack path stated 10 A cont. + 20 A fuse (09 \u00a72.3) vs 10 A fuse (05).", "ANNOTATION"], [1464, 616.56, 1488.804, 624.3599999999999, "05, 09", "ANNOTATION"], [804, 644.06, 820.5360000000001, 651.8599999999999, "OI-4", "ANNOTATION"], [844, 644.06, 926.6800000000001, 651.8599999999999, "Hall sensor location", "ANNOTATION"], [994, 644.06, 1452.874, 651.8599999999999, "On RB with mezzanine pin 66 (09 \u00a71, \u00a78.1) and on the MB J11 'Button/Hall flex' (09 \u00a79.1); the 3D viewer already", "ANNOTATION"], [994, 653.81, 1072.546, 661.6099999999999, "flags its position.", "ANNOTATION"], [1464, 644.06, 1505.34, 651.8599999999999, "09, viewer", "ANNOTATION"], [804, 671.56, 820.5360000000001, 679.3599999999999, "OI-5", "ANNOTATION"], [844, 671.56, 901.876, 679.3599999999999, "AON LDO source", "ANNOTATION"], [994, 671.56, 1237.906, 679.3599999999999, "05 \u00a74 feeds the 3.3 V AON LDO from VBAT; 09 \u00a75.1 from VSYS.", "ANNOTATION"], [1464, 671.56, 1488.804, 679.3599999999999, "05, 09", "ANNOTATION"], [804, 689.31, 820.5360000000001, 697.1099999999999, "OI-6", "ANNOTATION"], [844, 689.31, 930.814, 697.1099999999999, "VSYS bulk capacitance", "ANNOTATION"], [994, 689.31, 1270.978, 697.1099999999999, "2\u00d7 470 \u00b5F + 4\u00d7 22 \u00b5F (05 \u00a710.2) vs 2\u00d7 220 \u00b5F + 10\u00d7 10 \u00b5F (09 \u00a75.1).", "ANNOTATION"], [1464, 689.31, 1488.804, 697.1099999999999, "05, 09", "ANNOTATION"], [804, 707.06, 820.5360000000001, 714.8599999999999, "OI-7", "ANNOTATION"], [844, 707.06, 893.608, 714.8599999999999, "1.8 V source", "ANNOTATION"], [994, 707.06, 1320.586, 714.8599999999999, "1 A buck on MB (09 \u00a75.1, mezz pin 54) vs TLV75518 LDO with the readers (05 \u00a75).", "ANNOTATION"], [1464, 707.06, 1488.804, 714.8599999999999, "05, 09", "ANNOTATION"], [804, 724.81, 820.5360000000001, 732.6099999999999, "OI-8", "ANNOTATION"], [844, 724.81, 934.948, 732.6099999999999, "NTC channel allocation", "ANNOTATION"], [994, 724.81, 1432.2040000000002, 732.6099999999999, "02 \u00a78 NTC[5:0]: SoM boss, switch, CFe B cage, Ethernet PHY, battery, internal air; 06 \u00a76: skin #1, skin #2", "ANNOTATION"], [994, 734.56, 1448.74, 742.3599999999999, "(bottom band), front frame, internal air, battery \u00d72 via SMBus; 09 \u00a77: SoM edge, ASM2812, RTL8126, CFe B cage,", "ANNOTATION"], [994, 744.31, 1093.216, 752.1099999999999, "pack, spare; 10 BOM: \u00d74.", "ANNOTATION"], [1464, 724.81, 1521.876, 732.6099999999999, "02, 06, 09, 10", "ANNOTATION"], [804, 762.06, 820.5360000000001, 769.8599999999999, "OI-9", "ANNOTATION"], [844, 762.06, 959.752, 769.8599999999999, "Interlock latch enable sense", "ANNOTATION"], [994, 762.06, 1448.74, 769.8599999999999, "09 \u00a75.4 latches MUX_SEL with LE = NOT CFEB_PWR_EN_SENSE 'from the eFuse power-good', but the CFe B eFuse is on", "ANNOTATION"], [994, 771.81, 1428.0700000000002, 779.6099999999999, "the RB and the mezzanine allocation (09 \u00a78.1) has no PG/sense return pin \u2014 only the wired-OR SLOT_FAULT#.", "ANNOTATION"], [994, 781.56, 1229.638, 789.3599999999999, "Either sense the EC's CFEB_PWR_EN on the MB or add a pin.", "ANNOTATION"], [1464, 762.06, 1472.268, 769.8599999999999, "09", "ANNOTATION"], [804, 799.31, 824.67, 807.1099999999999, "OI-10", "ANNOTATION"], [844, 799.31, 922.546, 807.1099999999999, "SoM connector count", "ANNOTATION"], [994, 799.31, 1378.462, 807.1099999999999, "2\u00d7 B2B (09 \u00a71.1, \u00a79.1 J1/J2) vs 3\u00d7 B2B (04 \u00a7, 08 \u00a73.2). Moot if board-down is selected (D12).", "ANNOTATION"], [1464, 799.31, 1505.34, 807.1099999999999, "04, 08, 09", "ANNOTATION"], [804, 817.06, 824.67, 824.8599999999999, "OI-11", "ANNOTATION"], [844, 817.06, 881.206, 824.8599999999999, "RB length", "ANNOTATION"], [994, 817.06, 1262.71, 824.8599999999999, "180 \u00d7 38 mm (09 \u00a71 table) vs 172 mm (09 \u00a71.2, 08 \u00a73.1, drawings).", "ANNOTATION"], [1464, 817.06, 1488.804, 824.8599999999999, "08, 09", "ANNOTATION"], [804, 834.81, 824.67, 842.6099999999999, "OI-12", "ANNOTATION"], [844, 834.81, 922.546, 842.6099999999999, "Port C PD ownership", "ANNOTATION"], [994, 834.81, 1390.864, 842.6099999999999, "TPS25750-C owns CC with the ASM2464PD PD block passive (00 \u00a73.4) \u2014 verify with ASMedia (02 \u00a710).", "ANNOTATION"], [1464, 834.81, 1488.804, 842.6099999999999, "00, 02", "ANNOTATION"], [804, 852.56, 824.67, 860.3599999999999, "OI-13", "ANNOTATION"], [844, 852.56, 959.752, 860.3599999999999, "USB-C SuperSpeed orientation", "ANNOTATION"], [844, 862.31, 877.072, 870.1099999999999, "handling", "ANNOTATION"], [994, 852.56, 1444.606, 860.3599999999999, "No document states how plug-flip is handled on Ports A (RK3588 USBDP PHY) and B (ASM3142): PHY lane select vs", "ANNOTATION"], [994, 862.31, 1180.03, 870.1099999999999, "external SS mux. Drawn as 'orientation: TBD'.", "ANNOTATION"], [1464, 852.56, 1468.134, 860.3599999999999, "\u2014", "ANNOTATION"], [804, 880.06, 824.67, 887.8599999999999, "OI-14", "ANNOTATION"], [844, 880.06, 926.6800000000001, 887.8599999999999, "Reset pinhole switch", "ANNOTATION"], [994, 880.06, 1440.472, 887.8599999999999, "08 \u00a77 places a sealed reset tact on the bottom face; no connector or EC signal is listed in 09 \u00a79.1 / 02 \u00a78.", "ANNOTATION"], [994, 889.81, 1167.628, 897.6099999999999, "Drawn as MB-mounted, to EC GPIO (assumed).", "ANNOTATION"], [1464, 880.06, 1505.34, 887.8599999999999, "02, 08, 09", "ANNOTATION"], [804, 907.56, 824.67, 915.3599999999999, "OI-15", "ANNOTATION"], [844, 907.56, 955.618, 915.3599999999999, "LED bar location and supply", "ANNOTATION"], [994, 907.56, 1444.606, 915.3599999999999, "On RB (09 \u00a79.2 J7) with LED_DATA over mezzanine 67; 05 \u00a75 conditions its supply on \u2264 100 mA from the AON LDO,", "ANNOTATION"], [994, 917.31, 1407.4, 925.1099999999999, "else a 5 V driver \u2014 neither appears on the mezzanine allocation (3.3 V AON is not a mezzanine rail).", "ANNOTATION"], [1464, 907.56, 1488.804, 915.3599999999999, "05, 09", "ANNOTATION"], [804, 935.06, 824.67, 942.8599999999999, "OI-16", "ANNOTATION"], [844, 935.06, 951.484, 942.8599999999999, "Wi-Fi antenna cable length", "ANNOTATION"], [994, 935.06, 1423.9360000000001, 942.8599999999999, "09 \u00a74.2 caps the MHF4 cable at \u2264 120 mm; 07 \u00a74.3 routes WIFI0 at \u2248 140\u2013150 mm along the top rail (W-05).", "ANNOTATION"], [1464, 935.06, 1488.804, 942.8599999999999, "07, 09", "ANNOTATION"], [915, 993.4, 1353.8400000000001, 1005.4, "PoppyUp \u2014 Phase 1 Hardware Design \u2014 Wiring & Interconnect Diagram Set", "TITLE"], [915, 1015.8, 1201.4650000000001, 1027.3, "Cover, index, legend, general notes, open items", "TITLE"], [915, 1031.8, 1244.13, 1040.8, "Baseline: ADR v0.3 Generated from wiring/model.py + wiring/build.py", "TITLE"], [915, 1051.0, 1047.5, 1061.0, "Scale: NTS \u2014 NOT TO SCALE", "TITLE"], [915, 1067.8, 1253.67, 1076.8, "Units: mm where dimensioned Signal names per docs/02 \u00a78, docs/09 \u00a78\u20139", "TITLE"], [1265, 1014.6, 1361.46, 1027.6, "Sheet PU-W-000", "TITLE"], [1265, 1031.0, 1360.4, 1041.0, "Rev A 2026-09-27", "TITLE"], [1265, 1051.0, 1402.8, 1061.0, "Status: DRAFT \u2014 FOR REVIEW", "TITLE"], [1265, 1067.0, 1333.9, 1077.0, "Sheet 1 of 10", "TITLE"], [1430, 1017.8, 1549.25, 1026.8, "Prepared: hw architecture", "TITLE"], [1430, 1031.8, 1525.4, 1040.8, "(auto-generated set)", "TITLE"], [1430, 1051.8, 1482.47, 1060.8, "Reviewed: \u2014", "TITLE"], [1430, 1067.8, 1482.47, 1076.8, "Approved: \u2014", "TITLE"]], "ids": ["OI-1", "OI-10", "OI-11", "OI-12", "OI-13", "OI-14", "OI-15", "OI-16", "OI-2", "OI-3", "OI-4", "OI-5", "OI-6", "OI-7", "OI-8", "OI-9", "P-05", "P-nn", "W-05", "W-nn"], "frame": [40, 40, 1547, 1083]}