wiring/model.py
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# PoppyUp wiring set — structured source of truth (equipment, connectors, connections).# Every sheet and every schedule is generated from this file. Edit here, then run build.py.## Evidence classes used in `status`:# Verified — stated in an identified project document (docs/00–13) or a public standard# Derived — calculated/combined from identified inputs# Assumed — provisional drafting choice (must be confirmed at schematic capture)# TBD — insufficient information; left open on purpose# "Verified" here means verified against the PoppyUp design package, not against a vendor datasheet;# the package itself marks datasheet-dependent figures "(verify)". PROJECT = "PoppyUp — Phase 1 Hardware Design"SET_TITLE = "Wiring & Interconnect Diagram Set"REV = "A"BASELINE = "ADR v0.3"DATE = "2026-09-27"STATUS = "DRAFT — FOR REVIEW"PREFIX = "PU-W" # ---------------------------------------------------------------------------------------------# Equipment (boards, modules, sub-assemblies, external items)# ---------------------------------------------------------------------------------------------EQUIPMENT = { # id: (name, kind, location, source) "MB": ("Main board", "PCB 10L hybrid, 165 × 80 mm", "against rear Mg skin, Y 12–92", "09 §1"), "SOM": ("RK3588(J) SoM (Firefly Core-3588J default; Forlinx / board-down at PoC exit, D12)", "purchased module on MB J1/J2", "MB rear face, centred", "09 §1, 02 §4.1"), "RB": ("Reader daughterboard", "PCB 8L, 172 × 38 mm (09 §1 table says 180 × 38 — conflict)", "reader band, on MB front face via mezzanine", "09 §1, 08 §3.1"), "PACK": ("Battery pack sub-assembly (2S2P 21700, 72 Wh)", "certified sub-assembly", "battery band behind screw-down door", "05 §2.5"), "PB": ("Battery pack PCB", "PCB 2L, 60 × 25 mm", "inside PACK", "09 §1"), "WIFI": ("M.2 Key-E 2230 Wi-Fi 7 module (MediaTek MT7925)", "purchased module on MB J8", "MB rear face, X 140–162", "02 §4.6, 08 §3.1"), "NVME": ("M.2 M-key 2280 NVMe SSD (Pro SKU; socket empty on Base)", "purchased module on MB J9", "MB rear face, X 166–188", "02 §4.3, 08 §3.1"), "OLED": ("2.42\" 128 × 64 OLED module, SSD1309, SPI", "purchased module with FPC tail", "front frame, X 66.5–123.5, Y 10–40", "00 §3.7, 08 §3.1"), "BTNFLX": ("Button flex (power/action button, ring light pipe)", "flex circuit", "front frame, button at X 30, Y 12", "09 §1, §9.1 J11; 08 §7"), "ANTW0": ("Wi-Fi antenna WIFI0, tri-band flex element", "flex antenna, MHF4 pigtail", "front frame upper band, X 12–52, Y 30–38", "07 §4"), "ANTW1": ("Wi-Fi antenna WIFI1, tri-band flex element", "flex antenna, MHF4 pigtail", "front frame upper band, X 130–170, Y 30–38", "07 §4"), "THSW": ("Mechanical thermal switch (hardware backstop)", "discrete switch, 2 leads", "chassis inner wall — location TBD (06 §12 item 10)", "00 §3.5, 02 §8, 06 §7.2"), "FAN": ("Tunnel fan (reserved envelope, not fitted)", "future option", "chassis fan envelope", "09 §9.1 J17, ADR D5"), "CHASSIS":("Magnesium AZ91D chassis (ground reference)", "die-cast chassis", "rear and bottom skins", "09 §6, 08 §4.1"), "LEDBAR": ("5-segment RGB LED bar", "addressable LEDs on RB (baseline) or light-guide flex (alt.)", "front top edge over slot row", "09 §9.2 J7, 08 §3.1"), # external "EXT-A": ("Host / PD source on Port A (iPhone, Mac, PC, charger)", "external", "—", "00 §3.4"), "EXT-B": ("External SSD / tethered phone / USB cellular adapter on Port B", "external", "—", "00 §3.4"), "EXT-C": ("USB4 host / PD source on Port C (Pro SKU)", "external", "—", "00 §3.4"), "EXT-LAN":("5GBASE-T network", "external", "—", "00 §5"),} # ---------------------------------------------------------------------------------------------# Connectors — (equipment, ref): description, part class, positions, source# ---------------------------------------------------------------------------------------------CONNECTORS = { ("MB","J1"): ("SoM board-to-board (1 of 2)", "per SoM chosen at PoC exit; Firefly: 100-pin 0.5 mm B2B set (confirm count — 08 §3.2 says 3 connectors, 09 §1.1 says 2)", None, "09 §9.1"), ("MB","J2"): ("SoM board-to-board (2 of 2)", "as J1", None, "09 §9.1"), ("MB","J3"): ("Mezzanine to RB (male)", "Samtec ADM6-40-01.5-x-x-2, 80 pos., 0.635 mm", 80, "09 §8, §9.1"), ("MB","J4"): ("Port A USB-C 'PD / PHONE'", "IP67 mid-mount receptacle, USB 3.2 Gen1 + PD", 24, "09 §9.1, 08 §7"), ("MB","J5"): ("Port B USB-C 'SSD / TETHER'", "IP67 mid-mount receptacle, USB 3.2 Gen2 host, 5 V/3 A source", 24, "09 §9.1, 08 §7"), ("MB","J6"): ("Port C USB-C 'USB4 FAST' (Pro data + PD sink; blanked on Base)", "IP67 mid-mount receptacle, USB4 40 Gb/s rated (sourcing open, 09 §13)", 24, "09 §9.1, 08 §7"), ("MB","J7"): ("RJ45 5GBASE-T", "shielded tab-down through-hole, no magnetics (Amphenol RJHSE-5380 class); discrete Pulse H5007NL-class magnetics", 8, "09 §9.1, §3.5"), ("MB","J8"): ("M.2 Key-E 2230 socket (Wi-Fi)", "75-pos M.2, 4.2 mm", 75, "09 §9.1"), ("MB","J9"): ("M.2 M-key 2280 socket (NVMe, Pro)", "75-pos M.2, 4.2 mm", 75, "09 §9.1"), ("MB","J10"): ("OLED FPC", "30-pin 0.5 mm FPC (per SSD1309 module)", 30, "09 §9.1"), ("MB","J11"): ("Button/Hall flex", "6-pin 0.5 mm FPC", 6, "09 §9.1"), ("MB","J12"): ("Battery pack", "6-pin power connector with lock — family open: JST GH/XA class (09) vs Molex Micro-Fit / JST GH (05) vs Nano-Fit for 10 A (09)", 6, "09 §9.1, 05 §2.5"), ("MB","J13"): ("SoC debug UART", "4-pin 1.0 mm, unpopulated at PVT", 4, "09 §9.1, §10"), ("MB","J14"): ("EC SWD", "Tag-Connect TC2030 footprint, no component", 6, "09 §9.1"), ("MB","J15"): ("Spare PCIe Gen2 ×1 test header (pcie2x1l0)", "0.5 mm 20-pin FPC footprint, unpopulated", 20, "09 §9.1"), ("MB","J16"): ("Spare PCIe Gen2 ×1 test header (pcie2x1l2)", "0.5 mm 20-pin FPC footprint, unpopulated", 20, "09 §9.1"), ("MB","J17"): ("Fan header (reserved)", "3-pin 1.25 mm, unpopulated", 3, "09 §9.1"), ("MB","TP-OTG0"): ("RK3588 USB3 OTG0 maskrom test pads", "4-pin test pad group", 4, "09 §10"), ("MB","TP-USB2"): ("RK3588 USB 2.0 host 1 test pads", "4-pin test pad group", 4, "09 §9.1"), ("MB","TP-THSW"): ("Thermal-switch lead termination", "TBD (solder pads or 2-pin header) — not in 09 §9.1", 2, "TBD"), ("RB","J1"): ("CFexpress Type B slot", "push-push, deep insertion, metal cage, 10 k cycles", None, "09 §9.2"), ("RB","J2"): ("CFexpress Type A slot", "push-push, 10 k cycles", None, "09 §9.2"), ("RB","J3"): ("SD UHS-II slot", "17-pin push-push, deep insertion", 17, "09 §9.2"), ("RB","J4"): ("microSD slot", "push-push with card-detect", None, "09 §9.2"), ("RB","J5"): ("CFast 2.0 slot", "7 + 17 SATA-style receptacle, 5 k cycles", 24, "09 §9.2"), ("RB","J6"): ("Mezzanine to MB (female)", "Samtec ADF6-40-01.5-x-x-2, 80 pos.", 80, "09 §9.2"), ("RB","J7"): ("LED bar", "5× RGB addressable LEDs on-board, or 4-pin FPC to light-guide flex (decide at ID)", 4, "09 §9.2"), ("PB","J1"): ("Pack output (mates MB J12)", "as MB J12", 6, "09 §9.3"), ("PB","TABS"):("Cell tabs", "0.15 × 8 mm pure-nickel strip, spot-welded, soldered to pads", None, "05 §2.5"), ("WIFI","ANT0"): ("MHF4 receptacle (chain 0)", "I-PEX 20449 MHF4 on the module", 1, "07 §4.3"), ("WIFI","ANT1"): ("MHF4 receptacle (chain 1)", "I-PEX 20449 MHF4 on the module", 1, "07 §4.3"), ("OLED","FPC"): ("Module FPC tail", "30-pin 0.5 mm, module-supplied", 30, "09 §1"), ("BTNFLX","FPC"): ("Flex tail to MB J11", "6-pin 0.5 mm", 6, "09 §9.1"), ("ANTW0","PIG"): ("MHF4 pigtail plug", "1.37 mm coax, factory-fitted", 1, "07 §4.3"), ("ANTW1","PIG"): ("MHF4 pigtail plug", "1.37 mm coax, factory-fitted", 1, "07 §4.3"), ("THSW","LEADS"): ("Switch leads", "2 wires, TBD", 2, "TBD"),} # ---------------------------------------------------------------------------------------------# Connections. cls: POWER | HS (high-speed data) | CTRL (GPIO/discrete) | BUS (I2C/SMBus/SPI/UART) |# RF (coax) | BOND (chassis/ground bond) | MECH (mated module, no cable) | REF (reserved/alt)# Off-board items (cables, flexes, mated connectors) have medium != "PCB".# ---------------------------------------------------------------------------------------------def C(id, a, b, medium, signal, cls, sheets, status, source, notes="", length=""): return dict(id=id, frm=a, to=b, medium=medium, signal=signal, cls=cls, sheets=sheets, status=status, source=source, notes=notes, length=length) CONNECTIONS = [ # --- board-to-board / harness / flex (off-board) ------------------------------------------- C("W-01", ("MB","J3"), ("RB","J6"), "Direct mate, Samtec ADM6/ADF6 80-pin, stack 5–8 mm", "CFe B Gen3/Gen4 ×2 + REFCLK + sidebands; CFe A ×1; 3× Gen3 ×1 (GL9755/GL9750/ASM1064) + REFCLKs + PERST#; 3.3 V slots (8 pins) / 3.3 V logic (2) / 1.8 V (1); 5× PWR_EN; SLOT_FAULT#; SLOT_DET[4:0]; HALL; LED_DATA; I²C; NTC_CFEB; RB_PRESENT#; GND", "HS", ["101","201"], "Verified", "09 §8.1", "Logical allocation only; physical pin assignment finalised from connector S-parameters at layout (09 §8.1). Stack height set when 08 fixes RB-to-MB spacing (09 §13).", "0 (mated)"), C("W-02", ("PB","J1"), ("MB","J12"), "6-way discrete-wire pack harness with locking connector", "PACK+, PACK−, SMBus CLK, SMBus DAT, NTC, PRES#", "POWER", ["101","202","204"], "Verified", "05 §2.5, 09 §9.1", "Signal list from 05 §2.5. Connector family unresolved (see MB J12). Pack path rating: 10 A continuous / 20 A fuse (09 §2.3) vs 10 A chemical fuse, BQ40Z50 OCD 15 A (05 §2.5, §12) — reconcile. Battery negative bonded to MB GND at one point near the charger (09 §6).", "TBD (~60 mm est.)"), C("W-03", ("OLED","FPC"), ("MB","J10"), "Module-supplied 30-pin 0.5 mm FPC", "OLED_SPI (SCLK, SDIN), OLED_CS, OLED_DC, OLED_RST, VDD 3.3 V, VCC 12 V (boost, on MB or in module — 05 §5), GND", "BUS", ["101","204"], "Verified", "02 §8, 09 §9.1, 05 §5", "Pin numbers per the selected SSD1309 module datasheet — TBD. Connected at frame-marry step (08 §12 step 7).", "module tail"), C("W-04", ("BTNFLX","FPC"), ("MB","J11"), "6-pin 0.5 mm FPC (front-frame flex)", "BTN, button ring LED (if on flex), HALL (only if the Hall sensor is on the flex — conflict, see notes), 3.3 V AON, GND", "CTRL", ["101","204"], "Assumed", "09 §9.1 (J11 'Button/Hall flex'), 09 §1 (Hall on RB), 09 §8.1 pin 66", "Hall sensor is listed both on RB (mezzanine pin 66 HALL) and on the J11 flex. Baseline drawn: Hall on RB; J11 carries button + ring LED. Pin allocation is a proposal.", "TBD"), C("W-05", ("WIFI","ANT0"), ("ANTW0","PIG"), "MHF4 (I-PEX 20449) 1.37 mm coax", "Wi-Fi chain 0, 2.4 / 5 / 6 GHz", "RF", ["101","203"], "Verified", "07 §4.3", "≈ 140–150 mm along the chassis top rail; ≤ 0.35 dB at 6 GHz. Clipped every 30 mm; ≥ 10 mm from buck inductors; shield grounded to chassis within 10 mm of the element. ~30 mating cycles.", "140–150 mm (est.)"), C("W-06", ("WIFI","ANT1"), ("ANTW1","PIG"), "MHF4 (I-PEX 20449) 1.37 mm coax", "Wi-Fi chain 1, 2.4 / 5 / 6 GHz", "RF", ["101","203"], "Verified", "07 §4.3", "≈ 60 mm; ≤ 0.15 dB at 6 GHz. Same routing rules as W-05.", "≈ 60 mm (est.)"), C("W-07", ("RB","J7"), ("LEDBAR","—"), "On-board LEDs (baseline) or 4-pin FPC to light-guide flex (alternative)", "LED_DATA (serial addressable), 3.3 V AON or 5 V (TBD, 05 §5 LDO note), GND", "CTRL", ["101","204"], "TBD", "09 §9.2 J7, 09 §1, 05 §5", "Decide at industrial design. LED_DATA reaches RB over mezzanine pin 67. LED-bar supply: 3.3 V AON if peak ≤ 100 mA, else an LED driver from 5 V SYS (05 §5).", "—"), C("W-08", ("THSW","LEADS"), ("MB","TP-THSW"), "2 discrete leads, termination TBD", "THERM_ALERT to EC; contact in series with a circuit TBD (charge path / pack region, 06 §12 item 10)", "CTRL", ["101","103"], "TBD", "00 §3.5, 02 §8, 06 §7.2/§12", "Rating conflict: 48 °C (02 §8, 06 §7.2, 09 §7) vs '60 °C class, re-rated from 48 °C' (ADR 00 §3.5). Location and interrupted circuit fixed at EVT schematic release.", "TBD"), C("W-09", ("MB","J17"), ("FAN","—"), "Reserved 3-pin 1.25 mm header, unpopulated", "Fan supply (rail TBD), GND, TACH/PWM (TBD)", "REF", ["101","204"], "TBD", "09 §9.1, ADR D5", "Fan decision at the EVT-exit gate.", "—"), # --- mated modules (no cable) --------------------------------------------------------------- C("W-10", ("SOM","—"), ("MB","J1"), "Direct mate, SoM B2B connector set + 2× M2 retention screws", "pcie3x4 (Gen3 ×2 used), pcie3x2 (Gen3 ×2), pcie2x1l0/l1/l2, USB3 OTG0/OTG1, USB2 host ×2, SPI (TPM), UART/I²C/GPIO to EC, 5.0 V SYS in, GND", "MECH", ["101"], "Verified", "02 §3, 09 §9.1, §11", "J1/J2 do not exist if PoC exit selects board-down RK3588J (D12).", "—"), C("W-11", ("WIFI","—"), ("MB","J8"), "Direct mate, M.2 Key-E socket + chassis-pressed standoff", "PCIe Gen2 ×1 (pcie2x1l1) + REFCLK + PERST#/CLKREQ#/W_DISABLE#, USB 2.0 (BT, held in reset), 3.3 V LOGIC via LC π filter, GND", "MECH", ["101","203"], "Verified", "02 §4.4, 05 §5, 09 §11", "", "—"), C("W-12", ("NVME","—"), ("MB","J9"), "Direct mate, M.2 M-key socket + chassis-pressed standoff (Pro)", "PCIe Gen3 ×2 from ASM2812 + REFCLK + PERST#/CLKREQ#, 3.3 V via 2.5 A eFuse from 3.3 V SLOTS (or separate 3 A buck — EVT decision), GND", "MECH", ["101","203"], "Verified", "02 §4.3, 05 §3.2/§4, 09 §11", "Socket present on Base, module absent.", "—"), # --- external ports --------------------------------------------------------------------------- C("W-13", ("MB","J4"), ("EXT-A","—"), "User cable, USB-C", "USB 3.2 Gen1 device (RK3588 OTG1) + USB 2.0; PD sink 5–20 V ≤ 100 W accepted (input limit 3.3 A at 20 V); PD source 5 V/1.5 A (PR_Swap option)", "HS", ["101","203"], "Verified", "00 §3.3/3.4, 05 §7", "", "—"), C("W-14", ("MB","J5"), ("EXT-B","—"), "User cable, USB-C", "USB 3.2 Gen2 host (ASM3142) + USB 2.0; 5 V source 0.5 / 1.5 / 3 A (Rp set by EC; 3 A only with external PD present, D13)", "HS", ["101","203"], "Verified", "00 §3.3/3.4, 05 §7.4", "", "—"), C("W-15", ("MB","J6"), ("EXT-C","—"), "User cable, USB-C (USB4 40 Gb/s rated)", "USB4 device (ASM2464PD, USB 3.2 Gen2 UAS fallback) — Pro only; PD sink 5–20 V ≤ 3.25 A via priority mux — Pro only; Base: receptacle blanked, VBUS to attach-detect only", "HS", ["101","203"], "Verified", "00 §3.4, 05 §7.5", "", "—"), C("W-16", ("MB","J7"), ("EXT-LAN","—"), "Cat 6A patch cable", "5GBASE-T, 4 MDI pairs through discrete magnetics; hinged door (IP54 closed)", "HS", ["101","203"], "Verified", "00 §5, 09 §3.5, 08 §7", "", "—"), # --- chassis / ground bonds -------------------------------------------------------------------- C("W-17", ("MB","GND"), ("CHASSIS","—"), "8× screw bosses on exposed L1 GND rings (6 vias each); masked bare conversion-coated Mg; Zn-Ni steel or Al screws", "Chassis ground bond", "BOND", ["101"], "Verified", "09 §6, 08 §4.1", "Never stainless into Mg (D4). Contact resistance after 500 h salt fog — verify at EVT.", "—"), C("W-18", ("RB","GND"), ("CHASSIS","—"), "RB mounting rail + 5 cage pins", "Chassis ground bond; shutter and connector cages grounded to RB GND", "BOND", ["101"], "Verified", "09 §6, 08 §12 step 5", "", "—"), C("W-19", ("MB","J4/J5/J6/J7 shells"), ("CHASSIS","—"), "Receptacle brackets (Zn-Ni steel / Al) and RJ45 frame riveted to chassis wall", "Single-point-per-connector chassis bond; shells also to board GND at the connector", "BOND", ["101","203"], "Verified", "09 §6, 08 §7", "", "—"), C("W-20", ("PB","PACK−"), ("MB","GND"), "One-point bond near the charger", "Battery negative reference", "BOND", ["101","202"], "Verified", "09 §6", "", "—"), C("W-21", ("ANTW0","shield"), ("CHASSIS","—"), "Coax shield to chassis at the element end (feed PCB / EMI strip), within 10 mm of the element", "RF ground", "BOND", ["203"], "Verified", "07 §4.3", "Same for WIFI1.", "—"),] # ---------------------------------------------------------------------------------------------# On-board power distribution links (W-102). from/to are functional blocks on the MB unless noted.# ---------------------------------------------------------------------------------------------POWER_LINKS = [ # id, from, to, rail/voltage, current, cls-status, source, notes ("P-01", "J4 Port A VBUS", "TPS25750-A (CC/PD) and VBUS priority mux input A (Pro) / 0 Ω bypass (Base)", "VBUS 5–20 V", "≤ 3.25 A used (100 W tolerated)", "Verified", "05 §7.1, 09 §5.1", "TVS 24 V + OVP 22 V at the receptacle"), ("P-02", "J6 Port C VBUS", "TPS2121-class priority mux input B (Pro only)", "VBUS 5–20 V", "≤ 3.25 A (verify mux at 20 V / 65 W)", "Verified", "05 §7.5, 09 §5.1", "Base: VBUS pin to attach-detect divider + TVS only"), ("P-03", "VBUS priority mux output", "BQ25792 VBUS input", "VBUS_IN 5–20 V", "≤ 3.25 A", "Verified", "09 §5.1", "2× 22 µF + TVS at mux output; break-before-make gap ridden by charger input capacitance"), ("P-04", "J12 PACK+ / PACK−", "BQ25792 BAT", "VBAT 5.6–8.4 V (2S)", "5 A charge; system path 7 A; pack fuse 10 A", "Verified", "05 §2.5, §5, §8", "Trace sized for 2× fuse rating to the fuse (05 §12)"), ("P-05", "BQ25792 VSYS", "5.0 V SYS buck (TPS56637, 6 A)", "VSYS 6–8.4 V", "≤ 3.1 A out", "Verified", "05 §3.2, §5", "Bulk on VSYS: 2× 470 µF polymer + 4× 22 µF (05 §10.2) vs 2× 220 µF + 10× 10 µF (09 §5.1) — reconcile"), ("P-06", "BQ25792 VSYS", "5.0 V PORT B buck (TPS62933, 3 A)", "VSYS", "≤ 3 A out", "Verified", "05 §3.3, §5", "EN from EC; enabled only on Port B attach"), ("P-07", "BQ25792 VSYS", "3.3 V SLOTS buck (LMR33640, 4 A)", "VSYS", "≤ 3.85 A out (6 A class on Pro if NVMe fed from it)", "Verified", "05 §3.2, §5", ""), ("P-08", "BQ25792 VSYS", "3.3 V LOGIC buck (LMR33640, 4 A)", "VSYS", "≤ 3.1 A out (Pro peak)", "Verified", "05 §3.2, §5", "LC π filter at M.2 Key-E (< 20 mVpp)"), ("P-09", "VBAT (05 §4) / VSYS (09 §5.1) — conflict", "3.3 V AON LDO (TPS7A16, 100–150 mA)", "VBAT or VSYS", "≤ 120 mA", "Verified", "05 §4, §5, 09 §5.1", "05 feeds the AON LDO from VBAT (pack); 09 feeds it from VSYS. Drawn from VBAT (keeps EC alive with charger in ship mode); reconcile at schematic"), ("P-10", "3.3 V AON", "nRF5340 EC, Hall, RTC, SMBus pull-ups, LED bar (if ≤ 100 mA)", "3.3 V AON", "≤ 120 mA", "Verified", "05 §3.2, §11", "Coin cell MS621 (3 mAh) backs the RTC"), ("P-11", "5.0 V SYS", "SoM VIN via J1/J2", "5.0 V ±3 %", "≤ 1.6 A (8 W peak)", "Verified", "05 §3.2", "SoM's RK806 PMIC generates its own rails"), ("P-12", "5.0 V SYS", "Port A source eFuse 1.5 A → J4 VBUS (source role, PR_Swap phone top-up)", "5.0 V", "1.5 A", "Verified", "05 §4, §7.2", ""), ("P-13", "5.0 V SYS", "OLED VCC boost 12 V (TPS61041 class, or in module) → J10", "12 V", "~30 mA", "Verified", "05 §4, §5", ""), ("P-14", "5.0 V PORT B", "TPS2596 eFuse (3.3 A trip, EC ILIM 0.5/1.5/3 A) → J5 VBUS", "5.0 V", "0.5 / 1.5 / 3 A", "Verified", "05 §7.4", "Reverse-current blocking; VBUS applied only after Rp is set"), ("P-15", "3.3 V SLOTS", "J3 mezzanine pins 44–51 (8 pins) → RB slot eFuses", "3.3 V", "≥ 6 A total, 0.75 A/pin derated", "Verified", "09 §8.1", ""), ("P-16", "3.3 V SLOTS", "eFuse 2.5 A (Pro) → J9 M.2 NVMe 3.3 V", "3.3 V", "≤ 1.8 A", "Verified", "05 §3.2, §4", "Alternative: separate 3 A buck — EVT decision"), ("P-17", "RB 3.3 V slots (post-mezzanine)", "5× eFuse TPS2596 class → slots J1–J5", "3.3 V", "CFe B 2.5 / CFe A 1.5 / CFast 1.0 / SD 0.8 / µSD 0.5 A (09 §5.2) vs 2.0 / 1.2 / 1.2 / 0.5 / 0.3 A (05 §3.2, §4) — conflict", "Verified", "09 §5.2, 05 §3.2", "EN = PWR_EN from EC AND card-detect; soft-start 1–2 ms; active discharge on CFe B; fault wired-OR to SLOT_FAULT#"), ("P-18", "3.3 V LOGIC", "ASM2812 I/O + 1.05 V local buck (TPS62823)", "3.3 V / 1.05 V", "~1 A core", "Verified", "05 §4, 09 §5.1", "Point-of-load buck ≤ 15 mm from the chip"), ("P-19", "3.3 V LOGIC", "RTL8126 I/O + 1.05 V local buck", "3.3 V / 1.05 V", "≤ 1.5 A core", "Verified", "05 §4, 09 §5.1", ""), ("P-20", "3.3 V LOGIC", "ASM3142 + 1.05 V local buck", "3.3 V / 1.05 V", "—", "Verified", "05 §4, 09 §5.1", ""), ("P-21", "3.3 V LOGIC", "Load switch (ASM2464_PWR_EN from EC) → ASM2464PD + 1.05 V local buck + SPI flash (Pro)", "3.3 V / 1.05 V", "~1.2 A core", "Verified", "05 §7.5, 09 §5.1, 02 §6.1", "Bridge unpowered in standalone mode (zero draw)"), ("P-22", "3.3 V LOGIC", "J8 M.2 Key-E (MT7925) via LC π filter", "3.3 V", "≤ 0.75 A (2.5 W pk)", "Verified", "05 §5", ""), ("P-23", "3.3 V LOGIC", "PI3DBS16412 lane mux, HCSL clock mux, 74LVC1G373 latch, TPM SLB9672 (1.8 V I/O per 09 §5.1), PD controllers ×3", "3.3 V", "small", "Verified", "05 §4, 09 §5.1, §5.4", ""), ("P-24", "3.3 V LOGIC", "J3 mezzanine pins 52–53 → RB GL9755 / GL9750 / ASM1064 (+ RB 1.2 V ASM1064 core)", "3.3 V", "~0.4 A", "Verified", "09 §8.1, §2.2", ""), ("P-25", "1.8 V buck (1 A) on MB, fed from 3.3 V LOGIC (05 §3.2)", "UHS-II I/O (via mezzanine pin 54), TPM, misc I/O", "1.8 V", "0.6 A", "Verified", "09 §5.1, §8.1", "05 §5 lists a TLV75518 LDO for the readers' 1.8 V — one 1.8 V source, two documents; reconcile"),] # EC enable / supervision of the power tree (W-102 dashed control lines)POWER_CTRL = [ ("PMIC_EN", "EC → SoM PMIC (RK806) enable", "02 §8"), ("EN/PG 5 V SYS", "EC → TPS56637 EN, PG back", "05 §4"), ("EN + Rp select", "EC → TPS62933 EN; Rp / ILIM via PD-B and eFuse", "05 §4, §7.4"), ("EN 3.3 V SLOTS", "EC → LMR33640 EN", "05 §4"), ("EN 3.3 V LOGIC", "EC → LMR33640 EN", "05 §4"), ("ASM2464_PWR_EN", "EC → load switch (Pro)", "02 §8"), ("CFEB/CFEA/SD/USD/CFAST_PWR_EN", "EC → mezzanine 55–59 → RB eFuse EN", "09 §8.1"), ("PD_I2C", "EC ↔ TPS25750-A/B/C, BQ25792 (input-current limit, EN_HIZ)", "02 §8, 05 §7"), ("PACK_SMBUS", "EC ↔ BQ40Z50-R2 via J12", "02 §8"), ("VBUS_MUX_STAT / PORTC_PD_PRESENT", "mux / PD-C → EC (Pro)", "02 §8"),] # ---------------------------------------------------------------------------------------------# Mezzanine J3 (MB, male ADM6) ↔ J6 (RB, female ADF6) — logical allocation, 09 §8.1# (pins, group, count, MB side, RB side, notes)# ---------------------------------------------------------------------------------------------MEZZ_PINS = [ ("1–8", "CFe B PCIe lane 0/1 TX/RX (4 pairs)", 8, "PI3DBS16412 common port (Gen4-capable)", "J1 CFe B slot, L3 straight run ≤ 40 mm", "GND interleaved per Samtec ground pattern"), ("9–10", "CFe B REFCLK+/−", 2, "HCSL 2:1 clock mux output", "J1 CFe B REFCLK", "100 Ω HCSL"), ("11–13", "CFe B PERST#, CLKREQ#, WAKE#", 3, "EC GPIO (PERST# out; CLKREQ#/WAKE# in)", "J1 CFe B sideband", "EC forwards to SoC or ASM2464PD by mode"), ("14–17", "CFe A PCIe lane 0 TX/RX (2 pairs)", 4, "ASM2812 downstream port (Gen3 ×1)", "J2 CFe A slot", ""), ("18–19", "CFe A REFCLK", 2, "ASM2812 downstream REFCLK", "J2 CFe A", ""), ("20–22", "CFe A PERST#, CLKREQ#, WAKE#", 3, "ASM2812 downstream / EC GPIO (owner TBD at schematic)", "J2 CFe A sideband", ""), ("23–26", "GL9755 lane (2 pairs)", 4, "ASM2812 downstream (Gen3 ×1)", "GL9755 (SD UHS-II host)", ""), ("27–28", "GL9755 REFCLK", 2, "ASM2812", "GL9755", ""), ("29", "GL9755 PERST#", 1, "ASM2812 / EC (TBD)", "GL9755", ""), ("30–33", "GL9750 lane (2 pairs)", 4, "ASM2812 downstream (Gen3 ×1)", "GL9750 (microSD host)", ""), ("34–35", "GL9750 REFCLK", 2, "ASM2812", "GL9750", ""), ("36", "GL9750 PERST#", 1, "ASM2812 / EC (TBD)", "GL9750", ""), ("37–40", "ASM1064 lane (2 pairs)", 4, "ASM2812 downstream (Gen3 ×1)", "ASM1064 (AHCI SATA → CFast)", ""), ("41–42", "ASM1064 REFCLK", 2, "ASM2812", "ASM1064", ""), ("43", "ASM1064 PERST#", 1, "ASM2812 / EC (TBD)", "ASM1064", ""), ("44–51", "3.3 V SLOTS", 8, "3.3 V SLOTS buck output", "5× slot eFuse inputs", "≥ 6 A total, 0.75 A/pin derated"), ("52–53", "3.3 V LOGIC", 2, "3.3 V LOGIC buck", "GL9755 / GL9750 / ASM1064", ""), ("54", "1.8 V", 1, "1.8 V buck", "UHS-II I/O", ""), ("55–59", "CFEB / CFEA / SD / USD / CFAST_PWR_EN", 5, "EC GPIO out", "eFuse EN (AND card-detect)", ""), ("60", "SLOT_FAULT#", 1, "EC GPIO in", "wired-OR of 5 eFuse FLT#", ""), ("61–65", "SLOT_DET[4:0]", 5, "EC GPIO in (interrupt, wake)", "card-detect switches", ""), ("66", "HALL", 1, "EC GPIO in", "Hall sensor (shutter closed)", "see J11 conflict"), ("67", "LED_DATA", 1, "EC serial-LED out", "J7 LED bar", ""), ("68–69", "I²C SDA / SCL", 2, "EC I²C", "RB EEPROM (board ID / variant), eFuse telemetry", ""), ("70", "NTC_CFEB", 1, "EC ADC", "NTC at CFe B cage", "analog"), ("71", "RB_PRESENT#", 1, "EC GPIO in (pull-up)", "tied to GND on RB", ""), ("72–80", "GND", 9, "GND", "GND", "plus the connector's ground-pattern contacts — confirm pin numbering against the chosen ADM6/ADF6 variant"),] # ---------------------------------------------------------------------------------------------# EC signal wiring (W-103) — from 02 §8. (signal, dir from EC, type, far end, notes)# ---------------------------------------------------------------------------------------------EC_SIGNALS = [ # SoM ("EC_SOC_UART_TX/RX", "bidir", "UART 1 Mbaud, CRC-framed", "SOM", "mode events, display, thermal, battery, JOB_LOCATION, THERMAL_PAUSE_REQ/ACK/RESUME, PD_PRESENT"), ("EC_SOC_I2C", "target", "I²C 400 kHz", "SOM", "SoC reads EC registers"), ("PMIC_EN", "out", "GPIO", "SOM", "SoM PMIC enable"), ("SOC_RESET#", "out", "GPIO open-drain", "SOM", "hard reset"), ("SOC_HEARTBEAT", "in", "GPIO 1 Hz", "SOM", "watchdog (2 s)"), ("SOC_WAKE#", "out", "GPIO", "SOM", "wake from suspend"), ("SOC_CFEB_PERST_REQ#", "in", "GPIO", "SOM", "SoC root-port PERST request (mirrored by EC in standalone)"), ("CFEB_CLKREQ#/WAKE# → SoC", "out", "2× open-drain", "SOM", "forwarded from slot when SoC owns the card"), # mux / bridge ("MUX_SEL", "out", "GPIO → 74LVC1G373 D", "LATCH", "latched to PI3DBS16412 SEL only while CFEB_PWR_EN low"), ("REFCLK_SEL", "out", "GPIO", "CLKMUX", "separate pin for test; logically = MUX_SEL (via latch Q)"), ("CFEB_PERST#", "out", "GPIO", "J3 pin 11", "EC combines SOC_CFEB_PERST_REQ# or BR_CFEB_PERST# by mode"), ("BR_CFEB_PERST#", "in", "GPIO", "ASM2464PD", "bridge PERST output"), ("CFEB_CLKREQ#, CFEB_WAKE#", "in", "GPIO", "J3 pins 12–13", "from slot"), ("CFEB_CLKREQ#/WAKE# → bridge", "out", "2× open-drain", "ASM2464PD", "forwarded when bridge owns the card"), ("ASM2464_PWR_EN", "out", "GPIO", "LOADSW", "bridge 3.3 V load switch (Pro)"), # RB via mezzanine ("CFEB_PWR_EN", "out", "GPIO", "J3 pin 55", "slot eFuse enable; also the latch LE (inverted) — see note on W-104"), ("CFEA/SD/USD/CFAST_PWR_EN", "out", "4× GPIO", "J3 pins 56–59", ""), ("SLOT_DET[4:0]", "in", "5× GPIO int", "J3 pins 61–65", "wake source"), ("SLOT_FAULT#", "in", "GPIO", "J3 pin 60", "wired-OR eFuse fault"), ("HALL", "in", "GPIO", "J3 pin 66 (baseline) / J11 (alt.)", "shutter closed"), ("LED_DATA", "out", "serial LED", "J3 pin 67 → RB J7", "5-segment RGB bar"), ("EC_I2C (RB)", "ctrl", "I²C", "J3 pins 68–69", "RB EEPROM, eFuse telemetry"), ("NTC_CFEB", "in", "analog", "J3 pin 70", "CFe B cage"), ("RB_PRESENT#", "in", "GPIO", "J3 pin 71", ""), # PD / power ("PORTA_ATTACH / PORTB_ATTACH / PORTC_ATTACH", "in", "3× GPIO", "TPS25750-A / -B / -C", "attach/detach"), ("PORTB_VBUS_EN", "out", "GPIO", "TPS2596 Port B eFuse", ""), ("PORTB_ILIM", "out", "I²C reg + eFuse ILIM", "TPS25750-B / eFuse", "0.5 / 1.5 / 3 A; 3 A only with PD present (D13)"), ("PORTC_PD_PRESENT", "in", "GPIO / I²C", "TPS25750-C (Pro)", "gates PORTB_ILIM 3 A"), ("VBUS_MUX_STAT", "in", "GPIO", "TPS2121 mux (Pro)", "which input feeds the charger"), ("PD_I2C", "ctrl", "I²C", "TPS25750-A/-B/-C, BQ25792", ""), ("PACK_SMBUS", "ctrl", "SMBus 100 kHz", "J12 → BQ40Z50-R2", ""), ("Buck EN / PG", "out/in", "GPIO", "TPS56637, TPS62933, LMR33640 ×2", "rail sequencing"), ("VSYS_SENSE", "in", "ADC 1 kHz", "VSYS divider", "brown-out < 6.2 V for > 5 ms (05 §10.4)"), # sensors / UI / debug ("NTC[5:0]", "in", "6× analog", "NTCs", "SoM boss (skin #1), ASM2812, CFe B cage (via mezz 70), RTL8126 / bottom band (skin #2), battery (via pack), internal air — allocations differ between 02 §8, 06 §6, 09 §7 and 10 (×4); reconcile"), ("THERM_ALERT", "in", "GPIO", "THSW", "mechanical thermal switch"), ("OLED_SPI, OLED_CS, OLED_RST, OLED_DC", "out", "SPI", "J10", ""), ("BTN", "in", "GPIO", "J11", "series 1 kΩ + TVS"), ("RESET (pinhole)", "in", "GPIO", "MB-mounted sealed tact (08 §7)", "not in 09 connector table; assumed board-mounted"), ("EC_SWD", "debug", "SWD", "J14 Tag-Connect", "APPROTECT at PVT"), ("BLE 2.4 GHz", "RF", "chip antenna", "on-board (bottom-left)", "6 × 12 mm keep-out, PC window"),] # ---------------------------------------------------------------------------------------------# Proposed / documented small-connector pinouts (W-204). status per pinout.# ---------------------------------------------------------------------------------------------PINOUTS = { "J12 Battery pack (MB) / J1 (PB)": dict(status="Assumed (pin order); signal list Verified 05 §2.5", pins=[(1,"PACK+","to BQ25792 BAT; ≥ 5 A/pin — one pin per rail is only viable on a ≥ 5 A/pin family (Micro-Fit 3.0 / Nano-Fit); JST GH (1 A) / XA (3 A) cannot carry 5 A on one pin"), (2,"PACK−","one-point bond to MB GND near the charger"), (3,"SMB_CLK","BQ40Z50-R2 SMBus, pull-ups on 3.3 V AON"), (4,"SMB_DAT",""), (5,"NTC","pack NTC to BQ25792 TS (secondary, 05 §8); primary NTCs read by BQ40Z50"), (6,"PRES#","pack-present, tied to PACK− on PB (EC pull-up)")]), "J10 OLED FPC (MB) — 30-pin 0.5 mm": dict(status="Signals Verified (02 §8, 05 §5); pin numbers TBD per SSD1309 module datasheet", pins=[("—","GND",""),("—","VDD 3.3 V","logic"),("—","VCC 12 V","OLED panel supply (boost on MB or in module)"), ("—","OLED_SCLK","SPI"),("—","OLED_SDIN","SPI MOSI"),("—","OLED_CS#",""),("—","OLED_DC","data/command"),("—","OLED_RST#",""), ("—","(remaining pins)","per module: BS0–BS2 interface select tied for 4-wire SPI, VCOMH/IREF/VLSS caps, N.C.")]), "J11 Button flex (MB) — 6-pin 0.5 mm": dict(status="Assumed — proposal", pins=[(1,"GND",""),(2,"BTN","sealed tact to GND; series 1 kΩ + TVS on MB"),(3,"BTN_RING_LED","ring light-pipe LED (if on flex; else N.C.)"), (4,"HALL_OUT","only if the Hall sensor moves to the flex — baseline: N.C. (Hall on RB, mezz pin 66)"),(5,"3V3_AON",""),(6,"GND","")]), "J13 SoC debug UART (MB) — 4-pin 1.0 mm": dict(status="Assumed — proposal (unpopulated at PVT)", pins=[(1,"GND",""),(2,"SOC_UART_TX","1.8 V or 3.3 V level per SoM (verify)"),(3,"SOC_UART_RX",""),(4,"N.C. / VREF","")]), "J14 EC SWD — Tag-Connect TC2030 (ARM Cortex layout)": dict(status="Per Tag-Connect TC2030-CTX standard layout (verify against footprint drawing)", pins=[(1,"VTref 3.3 V AON",""),(2,"SWDIO",""),(3,"nRESET",""),(4,"SWCLK",""),(5,"GND",""),(6,"SWO","")]), "J17 Fan header (MB) — 3-pin 1.25 mm, unpopulated": dict(status="TBD — proposal", pins=[(1,"GND",""),(2,"FAN_V+","rail TBD (5.0 V SYS or VSYS)"),(3,"FAN_PWM/TACH","EC GPIO (TBD)")]), "TP-THSW Thermal switch (MB) — 2 pads": dict(status="TBD", pins=[(1,"THERM_ALERT","to EC GPIO (pull-up); switch contact"),(2,"GND / interrupted circuit","circuit interrupted at trip is TBD (06 §12 item 10)")]),} # ---------------------------------------------------------------------------------------------# Conflicts and open items surfaced while building the set (feeds W-000 and the validation report)# ---------------------------------------------------------------------------------------------OPEN_ITEMS = [ ("OI-1", "Thermal switch rating", "48 °C in 02 §8 / 06 §7.2 / 09 §7 vs '60 °C class, re-rated from 48 °C' in ADR 00 §3.5; location and interrupted circuit unspecified.", "00, 02, 06, 09"), ("OI-2", "Slot eFuse current limits", "09 §5.2: CFe B 2.5 / CFe A 1.5 / CFast 1.0 / SD 0.8 / µSD 0.5 A. 05 §3.2, §4: 2.0 / 1.2 / 1.2 / 0.5 / 0.3 A.", "05, 09"), ("OI-3", "Pack connector family and current per pin", "6-pin JST GH/XA (09) vs Molex Micro-Fit / JST GH (05); one pin each for PACK+/− must carry 5 A charge / 7 A system peaks; pack path stated 10 A cont. + 20 A fuse (09 §2.3) vs 10 A fuse (05).", "05, 09"), ("OI-4", "Hall sensor location", "On RB with mezzanine pin 66 (09 §1, §8.1) and on the MB J11 'Button/Hall flex' (09 §9.1); the 3D viewer already flags its position.", "09, viewer"), ("OI-5", "AON LDO source", "05 §4 feeds the 3.3 V AON LDO from VBAT; 09 §5.1 from VSYS.", "05, 09"), ("OI-6", "VSYS bulk capacitance", "2× 470 µF + 4× 22 µF (05 §10.2) vs 2× 220 µF + 10× 10 µF (09 §5.1).", "05, 09"), ("OI-7", "1.8 V source", "1 A buck on MB (09 §5.1, mezz pin 54) vs TLV75518 LDO with the readers (05 §5).", "05, 09"), ("OI-8", "NTC channel allocation", "02 §8 NTC[5:0]: SoM boss, switch, CFe B cage, Ethernet PHY, battery, internal air; 06 §6: skin #1, skin #2 (bottom band), front frame, internal air, battery ×2 via SMBus; 09 §7: SoM edge, ASM2812, RTL8126, CFe B cage, pack, spare; 10 BOM: ×4.", "02, 06, 09, 10"), ("OI-9", "Interlock latch enable sense", "09 §5.4 latches MUX_SEL with LE = NOT CFEB_PWR_EN_SENSE 'from the eFuse power-good', but the CFe B eFuse is on the RB and the mezzanine allocation (09 §8.1) has no PG/sense return pin — only the wired-OR SLOT_FAULT#. Either sense the EC's CFEB_PWR_EN on the MB or add a pin.", "09"), ("OI-10", "SoM connector count", "2× B2B (09 §1.1, §9.1 J1/J2) vs 3× B2B (04 §, 08 §3.2). Moot if board-down is selected (D12).", "04, 08, 09"), ("OI-11", "RB length", "180 × 38 mm (09 §1 table) vs 172 mm (09 §1.2, 08 §3.1, drawings).", "08, 09"), ("OI-12", "Port C PD ownership", "TPS25750-C owns CC with the ASM2464PD PD block passive (00 §3.4) — verify with ASMedia (02 §10).", "00, 02"), ("OI-13", "USB-C SuperSpeed orientation handling", "No document states how plug-flip is handled on Ports A (RK3588 USBDP PHY) and B (ASM3142): PHY lane select vs external SS mux. Drawn as 'orientation: TBD'.", "—"), ("OI-14", "Reset pinhole switch", "08 §7 places a sealed reset tact on the bottom face; no connector or EC signal is listed in 09 §9.1 / 02 §8. Drawn as MB-mounted, to EC GPIO (assumed).", "02, 08, 09"), ("OI-15", "LED bar location and supply", "On RB (09 §9.2 J7) with LED_DATA over mezzanine 67; 05 §5 conditions its supply on ≤ 100 mA from the AON LDO, else a 5 V driver — neither appears on the mezzanine allocation (3.3 V AON is not a mezzanine rail).", "05, 09"), ("OI-16", "Wi-Fi antenna cable length", "09 §4.2 caps the MHF4 cable at ≤ 120 mm; 07 §4.3 routes WIFI0 at ≈ 140–150 mm along the top rail (W-05).", "07, 09"),] SHEETS = [ ("000", "Cover, index, legend, general notes, open items"), ("101", "System interconnect — boards, modules, harnesses and external ports"), ("102", "Power distribution wiring"), ("103", "Embedded-controller control and sensor wiring"), ("104", "CFexpress B mode-switch path — lane mux, clock mux, interlock, USB4 bridge"), ("201", "Mezzanine J3 / J6 — 80-pin connection diagram"), ("202", "Battery pack sub-assembly wiring"), ("203", "External ports and M.2 module connector wiring"), ("204", "Peripheral connector pinouts — OLED, button flex, pack, debug, fan, thermal switch"), ("301", "Connection schedule"),] def sheet_no(n): return f"{PREFIX}-{n}"