wiring/README.md
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# PoppyUp — Wiring & Interconnect Diagram Set (Rev A, ADR v0.3, 2026-09-27) **Status: DRAFT — FOR REVIEW.** Logical wiring and connection diagrams for the Phase 1 hardware package: how the boards, modules, flexes, coax, pack harness and external ports connect, which signals cross each connector, and how power and control are distributed. Nothing here is a PCB layout or a measured installation drawing; the sheets are **not to scale** and imply no physical routing or cable length unless a length is stated with its basis. There is no CAD or schematic-capture tool in this environment, so the editable source is the generator (`model.py` + `build.py` + `src/w*.py`) and the SVG sheets it writes. The SVGs use named layers (`L-EQUIPMENT`, `L-CONN-POWER`, …) and open in Inkscape / Illustrator / draw.io. They carry **no netlist**; ERC belongs to the EVT schematic capture. ## Sheets | Sheet | Title | Content ||---|---|---|| PU-W-000 | Cover, index, legend, general notes, open items | Conventions, evidence classes, 16 source-document conflicts found while drafting (OI-1…OI-16) || PU-W-101 | System interconnect | Every board, module, flex, coax, harness, bond and external port; connections W-01…W-20 || PU-W-102 | Power distribution wiring | Port A/C VBUS → PD controllers → priority mux → BQ25792 ← pack; VSYS → bucks → rails → consumers; slot eFuses; EC enables; P-01…P-25 || PU-W-103 | EC control and sensor wiring | Every nRF5340 signal of docs/02 §8 to its far end: SoM, mode-switch group, mezzanine, PD/power, sensors, UI, debug || PU-W-104 | CFexpress B mode-switch path | Lane mux, HCSL clock mux, 74LVC1G373 interlock, sideband ownership, CFe B eFuse, ASM2464PD and Port C || PU-W-201 | Mezzanine J3 / J6 | The 80-pin ADM6/ADF6 allocation of docs/09 §8.1 as a connection diagram, both sides || PU-W-202 | Battery pack sub-assembly | 2S2P cells, nickel bus, BQ40Z50-R2, BQ294xx + fuse, NTCs, J1 pinout (pin order proposed), harness W-02 || PU-W-203 | External ports and M.2 modules | USB-C A/B/C signal usage, RJ45 → magnetics → RTL8126 MDI, M.2 Key-E and M-key signal groups, MHF4 coax || PU-W-204 | Peripheral connector pinouts | J10 OLED, J11 button flex, J12 pack, J13 UART, J14 SWD, J17 fan, thermal-switch pads — each with its evidence status || PU-W-301 | Connection schedule | Off-board connections W-01…W-21 with medium, signal, class, length basis, status, source, sheets | Files: `sheets/PU-W-xxx.svg` (editable source), `preview/PU-W-xxx.png` (headless-Chrome renders), `PU_Wiring-Set_Rev-A.pdf` (all sheets, A3 landscape), `PU_Connection-Schedule_Rev-A.csv` / `.md`, `PU_Validation_Rev-A.md`. ## Regenerate ```bashpython3 wiring/build.py # SVGs + schedules from model.pyPUPPETEER_DIR=/tmp/pu3d-tools node wiring/render.mjs # PNG previews + combined PDF (needs puppeteer-core + local Chrome, as for viewer/test)python3 wiring/validate.py # structural + render checks → PU_Validation_Rev-A.md``` `python3 wiring/build.py 102` builds one sheet; `node wiring/render.mjs 102` renders one preview. ## Evidence register | Class | Meaning | Where it applies ||---|---|---|| **Verified** | stated in docs/00–13 or a named public standard (USB-C pin names, T568 pairs, Tag-Connect TC2030 layout) | connector refs, signal names, rails, ratings, mezzanine allocation, lengths of MHF4 coax (docs/07 estimates) || **Derived** | combined from stated inputs | pin-count totals, class-per-signal || **Assumed** | drafting proposal — confirm at EVT schematic capture | pin *order* of J12 pack, J11 button flex, J13 UART, J17 fan; Hall-on-RB baseline; reset switch board-mounted || **TBD** | insufficient information | thermal-switch rating/location/circuit, fan header signals, LED-bar location, OLED pin numbers, USB-C SuperSpeed orientation handling | "Verified" means verified against the PoppyUp design package, not against a vendor datasheet; the package itself marks datasheet-dependent figures "(verify)". No manufacturer pinout, cable rating or protection setting has been invented; where the docs are silent the sheet says TBD. ## Source-document conflicts surfaced by this set Drafting a connection diagram forces every rail, pin and part to agree across documents. These did not (full list on PU-W-000 and in `PU_Validation_Rev-A.md`; candidates for the next ADR revision, see `docs/00` §15 workflow): - **OI-1** thermal switch 48 °C (02/06/09) vs "60 °C class" (ADR §3.5); location and interrupted circuit unspecified.- **OI-2** slot eFuse limits differ between 09 §5.2 and 05 §3.2/§4.- **OI-3** pack connector family and per-pin current: a 6-pin allocation with one PACK+ and one PACK− pin needs a ≥ 5 A/pin family; JST GH/XA cannot; 10 A vs 20 A fuse statements.- **OI-4** Hall sensor on the RB (mezz pin 66) *and* on the J11 flex.- **OI-5 / OI-6 / OI-7** AON LDO fed from VBAT (05) vs VSYS (09); VSYS bulk capacitance; 1.8 V from buck (09) vs LDO (05).- **OI-8** NTC channel allocation differs between 02 §8, 06 §6, 09 §7 and the BOM count.- **OI-9** the mode-switch interlock latch needs the CFe B eFuse power-good, but the eFuse is on the RB and the mezzanine has no PG return pin.- **OI-10 / OI-11** SoM connector count 2 vs 3; RB length 172 vs 180 mm.- **OI-12 … OI-16** Port C PD ownership (verify with ASMedia), USB-C plug-flip handling not documented, reset pinhole switch has no connector/EC signal, LED-bar supply not on the mezzanine, Wi-Fi coax length ≤ 120 mm (09) vs 140–150 mm (07). ## Limitations - SVG only: no DXF/DWG, no native schematic, no netlist or ERC. If the package acquires a KiCad/Altium project, `model.py` is the seed for its connector and net tables.- Cable lengths are estimates from the docs/08 layout (marked "est.") or TBD; none are measured or derived from routed geometry.- On-board IC placements on PU-W-102/103/104 are functional, not physical.- Text-overlap detection in `validate.py` is a bounding-box heuristic; the PNG previews are the visual record.