wiring/PU_Validation_Rev-A.md
5.4 KB · 57 lines · markdown · View rendered · Download from the repository page
# PoppyUp wiring set — validation report (Rev A, 2026-09-27) Baseline ADR v0.3. Status **DRAFT — FOR REVIEW**. Generated by `wiring/validate.py` after `build.py` and `render.mjs`. | # | Check | Result | Detail ||---|---|---|---|| 1 | Unique connection / link / open-item IDs | **PASS** | 62 IDs || 2 | Every connection references existing equipment and connectors | **PASS** | 21 connections || 3 | Connection sheet cross-references resolve | **PASS** | all resolve || 4 | Mezzanine allocation totals 80 pins | **PASS** | 80 pins across 27 groups || 5 | Pack pinout matches J12 position count | **PASS** | 6 positions || 6 | Every sheet in the index exists as an SVG | **PASS** | 10 files; missing [], extra [] || 7 | Geometry inside the sheet bounds (1587 × 1123) | **PASS** | 0 out-of-bounds primitives || 8 | Connection IDs appear on every sheet they are assigned to | **PASS** | all present || 9 | Estimated text-bbox overlaps (heuristic, 0.53 em advance) | **WARN** | 2 candidate overlaps — see per-sheet list; confirmed visually on PNG previews || 10 | Annotation text inside the drawing frame | **PASS** | 0 texts outside the frame || 11 | PNG preview rendered for every sheet (headless Chrome) | **PASS** | 10 PNG / 10 SVG || 12 | Combined PDF page count equals sheet count | **PASS** | 10 pages / 10 sheets, 1061 kB || 13 | Electrical rule check / netlist | **NOT APPLICABLE** | SVG diagrams carry no netlist; ERC belongs to the EVT schematic capture || 14 | Native CAD (DXF/DWG) export | **NOT RUN** | no CAD tool or ezdxf available in this environment; SVG is the editable source | ## Per-sheet render checks | Sheet | Out-of-bounds primitives | Text-overlap candidates | Examples ||---|---|---|---|| PU-W-000.svg | 0 | 0 | — || PU-W-101.svg | 0 | 0 | — || PU-W-102.svg | 0 | 0 | — || PU-W-103.svg | 0 | 0 | — || PU-W-104.svg | 0 | 0 | — || PU-W-201.svg | 0 | 0 | — || PU-W-202.svg | 0 | 2 | “A+ (nickel strip bus, 0.15 × 8 mm, spot” ↔ “B+ = PACK+ node (7.2 V nom., 8.4 V max)”; “NTC 2 10 k” ↔ “2× 10 k NTC glued to the cell cans, one ” || PU-W-203.svg | 0 | 0 | — || PU-W-204.svg | 0 | 0 | — || PU-W-301.svg | 0 | 0 | — | ## Open items carried on PU-W-000 - **OI-1 Thermal switch rating** — 48 °C in 02 §8 / 06 §7.2 / 09 §7 vs '60 °C class, re-rated from 48 °C' in ADR 00 §3.5; location and interrupted circuit unspecified. (docs 00, 02, 06, 09)- **OI-2 Slot eFuse current limits** — 09 §5.2: CFe B 2.5 / CFe A 1.5 / CFast 1.0 / SD 0.8 / µSD 0.5 A. 05 §3.2, §4: 2.0 / 1.2 / 1.2 / 0.5 / 0.3 A. (docs 05, 09)- **OI-3 Pack connector family and current per pin** — 6-pin JST GH/XA (09) vs Molex Micro-Fit / JST GH (05); one pin each for PACK+/− must carry 5 A charge / 7 A system peaks; pack path stated 10 A cont. + 20 A fuse (09 §2.3) vs 10 A fuse (05). (docs 05, 09)- **OI-4 Hall sensor location** — On RB with mezzanine pin 66 (09 §1, §8.1) and on the MB J11 'Button/Hall flex' (09 §9.1); the 3D viewer already flags its position. (docs 09, viewer)- **OI-5 AON LDO source** — 05 §4 feeds the 3.3 V AON LDO from VBAT; 09 §5.1 from VSYS. (docs 05, 09)- **OI-6 VSYS bulk capacitance** — 2× 470 µF + 4× 22 µF (05 §10.2) vs 2× 220 µF + 10× 10 µF (09 §5.1). (docs 05, 09)- **OI-7 1.8 V source** — 1 A buck on MB (09 §5.1, mezz pin 54) vs TLV75518 LDO with the readers (05 §5). (docs 05, 09)- **OI-8 NTC channel allocation** — 02 §8 NTC[5:0]: SoM boss, switch, CFe B cage, Ethernet PHY, battery, internal air; 06 §6: skin #1, skin #2 (bottom band), front frame, internal air, battery ×2 via SMBus; 09 §7: SoM edge, ASM2812, RTL8126, CFe B cage, pack, spare; 10 BOM: ×4. (docs 02, 06, 09, 10)- **OI-9 Interlock latch enable sense** — 09 §5.4 latches MUX_SEL with LE = NOT CFEB_PWR_EN_SENSE 'from the eFuse power-good', but the CFe B eFuse is on the RB and the mezzanine allocation (09 §8.1) has no PG/sense return pin — only the wired-OR SLOT_FAULT#. Either sense the EC's CFEB_PWR_EN on the MB or add a pin. (docs 09)- **OI-10 SoM connector count** — 2× B2B (09 §1.1, §9.1 J1/J2) vs 3× B2B (04 §, 08 §3.2). Moot if board-down is selected (D12). (docs 04, 08, 09)- **OI-11 RB length** — 180 × 38 mm (09 §1 table) vs 172 mm (09 §1.2, 08 §3.1, drawings). (docs 08, 09)- **OI-12 Port C PD ownership** — TPS25750-C owns CC with the ASM2464PD PD block passive (00 §3.4) — verify with ASMedia (02 §10). (docs 00, 02)- **OI-13 USB-C SuperSpeed orientation handling** — No document states how plug-flip is handled on Ports A (RK3588 USBDP PHY) and B (ASM3142): PHY lane select vs external SS mux. Drawn as 'orientation: TBD'. (docs —)- **OI-14 Reset pinhole switch** — 08 §7 places a sealed reset tact on the bottom face; no connector or EC signal is listed in 09 §9.1 / 02 §8. Drawn as MB-mounted, to EC GPIO (assumed). (docs 02, 08, 09)- **OI-15 LED bar location and supply** — On RB (09 §9.2 J7) with LED_DATA over mezzanine 67; 05 §5 conditions its supply on ≤ 100 mA from the AON LDO, else a 5 V driver — neither appears on the mezzanine allocation (3.3 V AON is not a mezzanine rail). (docs 05, 09)- **OI-16 Wi-Fi antenna cable length** — 09 §4.2 caps the MHF4 cable at ≤ 120 mm; 07 §4.3 routes WIFI0 at ≈ 140–150 mm along the top rail (W-05). (docs 07, 09) Result key: PASS / FAIL / WARN / NOT RUN / NOT APPLICABLE. A WARN on the text-overlap heuristic is not a defect by itself; the PNG previews in `wiring/preview/` are the visual record.