wiring/PU_Connection-Schedule_Rev-A.csv

1ID,From equipment,From connector,To equipment,To connector,Medium,Signal / service,Class,Length,Status,Source,Sheets,Notes
2W-01,Main board,J3,Reader daughterboard,J6,"Direct mate, Samtec ADM6/ADF6 80-pin, stack 5–8 mm",CFe B Gen3/Gen4 ×2 + REFCLK + sidebands; CFe A ×1; 3× Gen3 ×1 (GL9755/GL9750/ASM1064) + REFCLKs + PERST#; 3.3 V slots (8 pins) / 3.3 V logic (2) / 1.8 V (1); 5× PWR_EN; SLOT_FAULT#; SLOT_DET[4:0]; HALL; LED_DATA; I²C; NTC_CFEB; RB_PRESENT#; GND,HS,0 (mated),Verified,09 §8.1,PU-W-101 PU-W-201,Logical allocation only; physical pin assignment finalised from connector S-parameters at layout (09 §8.1). Stack height set when 08 fixes RB-to-MB spacing (09 §13).
3W-02,Battery pack PCB,J1,Main board,J12,6-way discrete-wire pack harness with locking connector,"PACK+, PACK−, SMBus CLK, SMBus DAT, NTC, PRES#",POWER,TBD (~60 mm est.),Verified,"05 §2.5, 09 §9.1",PU-W-101 PU-W-202 PU-W-204,"Signal list from 05 §2.5. Connector family unresolved (see MB J12). Pack path rating: 10 A continuous / 20 A fuse (09 §2.3) vs 10 A chemical fuse, BQ40Z50 OCD 15 A (05 §2.5, §12) — reconcile. Battery negative bonded to MB GND at one point near the charger (09 §6)."
4W-03,"2.42"" 128 × 64 OLED module, SSD1309, SPI",FPC,Main board,J10,Module-supplied 30-pin 0.5 mm FPC,"OLED_SPI (SCLK, SDIN), OLED_CS, OLED_DC, OLED_RST, VDD 3.3 V, VCC 12 V (boost, on MB or in module — 05 §5), GND",BUS,module tail,Verified,"02 §8, 09 §9.1, 05 §5",PU-W-101 PU-W-204,Pin numbers per the selected SSD1309 module datasheet — TBD. Connected at frame-marry step (08 §12 step 7).
5W-04,"Button flex (power/action button, ring light pipe)",FPC,Main board,J11,6-pin 0.5 mm FPC (front-frame flex),"BTN, button ring LED (if on flex), HALL (only if the Hall sensor is on the flex — conflict, see notes), 3.3 V AON, GND",CTRL,TBD,Assumed,"09 §9.1 (J11 'Button/Hall flex'), 09 §1 (Hall on RB), 09 §8.1 pin 66",PU-W-101 PU-W-204,Hall sensor is listed both on RB (mezzanine pin 66 HALL) and on the J11 flex. Baseline drawn: Hall on RB; J11 carries button + ring LED. Pin allocation is a proposal.
6W-05,M.2 Key-E 2230 Wi-Fi 7 module (MediaTek MT7925),ANT0,"Wi-Fi antenna WIFI0, tri-band flex element",PIG,MHF4 (I-PEX 20449) 1.37 mm coax,"Wi-Fi chain 0, 2.4 / 5 / 6 GHz",RF,140–150 mm (est.),Verified,07 §4.3,PU-W-101 PU-W-203,≈ 140–150 mm along the chassis top rail; ≤ 0.35 dB at 6 GHz. Clipped every 30 mm; ≥ 10 mm from buck inductors; shield grounded to chassis within 10 mm of the element. ~30 mating cycles.
7W-06,M.2 Key-E 2230 Wi-Fi 7 module (MediaTek MT7925),ANT1,"Wi-Fi antenna WIFI1, tri-band flex element",PIG,MHF4 (I-PEX 20449) 1.37 mm coax,"Wi-Fi chain 1, 2.4 / 5 / 6 GHz",RF,≈ 60 mm (est.),Verified,07 §4.3,PU-W-101 PU-W-203,≈ 60 mm; ≤ 0.15 dB at 6 GHz. Same routing rules as W-05.
8W-07,Reader daughterboard,J7,5-segment RGB LED bar,—,On-board LEDs (baseline) or 4-pin FPC to light-guide flex (alternative),"LED_DATA (serial addressable), 3.3 V AON or 5 V (TBD, 05 §5 LDO note), GND",CTRL,—,TBD,"09 §9.2 J7, 09 §1, 05 §5",PU-W-101 PU-W-204,"Decide at industrial design. LED_DATA reaches RB over mezzanine pin 67. LED-bar supply: 3.3 V AON if peak ≤ 100 mA, else an LED driver from 5 V SYS (05 §5)."
9W-08,Mechanical thermal switch (hardware backstop),LEADS,Main board,TP-THSW,"2 discrete leads, termination TBD","THERM_ALERT to EC; contact in series with a circuit TBD (charge path / pack region, 06 §12 item 10)",CTRL,TBD,TBD,"00 §3.5, 02 §8, 06 §7.2/§12",PU-W-101 PU-W-103,"Rating conflict: 48 °C (02 §8, 06 §7.2, 09 §7) vs '60 °C class, re-rated from 48 °C' (ADR 00 §3.5). Location and interrupted circuit fixed at EVT schematic release."
10W-09,Main board,J17,"Tunnel fan (reserved envelope, not fitted)",—,"Reserved 3-pin 1.25 mm header, unpopulated","Fan supply (rail TBD), GND, TACH/PWM (TBD)",REF,—,TBD,"09 §9.1, ADR D5",PU-W-101 PU-W-204,Fan decision at the EVT-exit gate.
11W-10,"RK3588(J) SoM (Firefly Core-3588J default; Forlinx / board-down at PoC exit, D12)",—,Main board,J1,"Direct mate, SoM B2B connector set + 2× M2 retention screws","pcie3x4 (Gen3 ×2 used), pcie3x2 (Gen3 ×2), pcie2x1l0/l1/l2, USB3 OTG0/OTG1, USB2 host ×2, SPI (TPM), UART/I²C/GPIO to EC, 5.0 V SYS in, GND",MECH,—,Verified,"02 §3, 09 §9.1, §11",PU-W-101,J1/J2 do not exist if PoC exit selects board-down RK3588J (D12).
12W-11,M.2 Key-E 2230 Wi-Fi 7 module (MediaTek MT7925),—,Main board,J8,"Direct mate, M.2 Key-E socket + chassis-pressed standoff","PCIe Gen2 ×1 (pcie2x1l1) + REFCLK + PERST#/CLKREQ#/W_DISABLE#, USB 2.0 (BT, held in reset), 3.3 V LOGIC via LC π filter, GND",MECH,—,Verified,"02 §4.4, 05 §5, 09 §11",PU-W-101 PU-W-203,
13W-12,M.2 M-key 2280 NVMe SSD (Pro SKU; socket empty on Base),—,Main board,J9,"Direct mate, M.2 M-key socket + chassis-pressed standoff (Pro)","PCIe Gen3 ×2 from ASM2812 + REFCLK + PERST#/CLKREQ#, 3.3 V via 2.5 A eFuse from 3.3 V SLOTS (or separate 3 A buck — EVT decision), GND",MECH,—,Verified,"02 §4.3, 05 §3.2/§4, 09 §11",PU-W-101 PU-W-203,"Socket present on Base, module absent."
14W-13,Main board,J4,"Host / PD source on Port A (iPhone, Mac, PC, charger)",—,"User cable, USB-C",USB 3.2 Gen1 device (RK3588 OTG1) + USB 2.0; PD sink 5–20 V ≤ 100 W accepted (input limit 3.3 A at 20 V); PD source 5 V/1.5 A (PR_Swap option),HS,—,Verified,"00 §3.3/3.4, 05 §7",PU-W-101 PU-W-203,
15W-14,Main board,J5,External SSD / tethered phone / USB cellular adapter on Port B,—,"User cable, USB-C","USB 3.2 Gen2 host (ASM3142) + USB 2.0; 5 V source 0.5 / 1.5 / 3 A (Rp set by EC; 3 A only with external PD present, D13)",HS,—,Verified,"00 §3.3/3.4, 05 §7.4",PU-W-101 PU-W-203,
16W-15,Main board,J6,USB4 host / PD source on Port C (Pro SKU),—,"User cable, USB-C (USB4 40 Gb/s rated)","USB4 device (ASM2464PD, USB 3.2 Gen2 UAS fallback) — Pro only; PD sink 5–20 V ≤ 3.25 A via priority mux — Pro only; Base: receptacle blanked, VBUS to attach-detect only",HS,—,Verified,"00 §3.4, 05 §7.5",PU-W-101 PU-W-203,
17W-16,Main board,J7,5GBASE-T network,—,Cat 6A patch cable,"5GBASE-T, 4 MDI pairs through discrete magnetics; hinged door (IP54 closed)",HS,—,Verified,"00 §5, 09 §3.5, 08 §7",PU-W-101 PU-W-203,
18W-17,Main board,GND,Magnesium AZ91D chassis (ground reference),—,8× screw bosses on exposed L1 GND rings (6 vias each); masked bare conversion-coated Mg; Zn-Ni steel or Al screws,Chassis ground bond,BOND,—,Verified,"09 §6, 08 §4.1",PU-W-101,Never stainless into Mg (D4). Contact resistance after 500 h salt fog — verify at EVT.
19W-18,Reader daughterboard,GND,Magnesium AZ91D chassis (ground reference),—,RB mounting rail + 5 cage pins,Chassis ground bond; shutter and connector cages grounded to RB GND,BOND,—,Verified,"09 §6, 08 §12 step 5",PU-W-101,
20W-19,Main board,J4/J5/J6/J7 shells,Magnesium AZ91D chassis (ground reference),—,Receptacle brackets (Zn-Ni steel / Al) and RJ45 frame riveted to chassis wall,Single-point-per-connector chassis bond; shells also to board GND at the connector,BOND,—,Verified,"09 §6, 08 §7",PU-W-101 PU-W-203,
21W-20,Battery pack PCB,PACK−,Main board,GND,One-point bond near the charger,Battery negative reference,BOND,—,Verified,09 §6,PU-W-101 PU-W-202,
22W-21,"Wi-Fi antenna WIFI0, tri-band flex element",shield,Magnesium AZ91D chassis (ground reference),—,"Coax shield to chassis at the element end (feed PCB / EMI strip), within 10 mm of the element",RF ground,BOND,—,Verified,07 §4.3,PU-W-203,Same for WIFI1.
23
24On-board power links (main board unless noted)
25ID,From,To,Rail / voltage,Current,Status,Source,Notes
26P-01,J4 Port A VBUS,TPS25750-A (CC/PD) and VBUS priority mux input A (Pro) / 0 Ω bypass (Base),VBUS 5–20 V,≤ 3.25 A used (100 W tolerated),Verified,"05 §7.1, 09 §5.1",TVS 24 V + OVP 22 V at the receptacle
27P-02,J6 Port C VBUS,TPS2121-class priority mux input B (Pro only),VBUS 5–20 V,≤ 3.25 A (verify mux at 20 V / 65 W),Verified,"05 §7.5, 09 §5.1",Base: VBUS pin to attach-detect divider + TVS only
28P-03,VBUS priority mux output,BQ25792 VBUS input,VBUS_IN 5–20 V,≤ 3.25 A,Verified,09 §5.1,2× 22 µF + TVS at mux output; break-before-make gap ridden by charger input capacitance
29P-04,J12 PACK+ / PACK−,BQ25792 BAT,VBAT 5.6–8.4 V (2S),5 A charge; system path 7 A; pack fuse 10 A,Verified,"05 §2.5, §5, §8",Trace sized for 2× fuse rating to the fuse (05 §12)
30P-05,BQ25792 VSYS,"5.0 V SYS buck (TPS56637, 6 A)",VSYS 6–8.4 V,≤ 3.1 A out,Verified,"05 §3.2, §5",Bulk on VSYS: 2× 470 µF polymer + 4× 22 µF (05 §10.2) vs 2× 220 µF + 10× 10 µF (09 §5.1) — reconcile
31P-06,BQ25792 VSYS,"5.0 V PORT B buck (TPS62933, 3 A)",VSYS,≤ 3 A out,Verified,"05 §3.3, §5",EN from EC; enabled only on Port B attach
32P-07,BQ25792 VSYS,"3.3 V SLOTS buck (LMR33640, 4 A)",VSYS,≤ 3.85 A out (6 A class on Pro if NVMe fed from it),Verified,"05 §3.2, §5",
33P-08,BQ25792 VSYS,"3.3 V LOGIC buck (LMR33640, 4 A)",VSYS,≤ 3.1 A out (Pro peak),Verified,"05 §3.2, §5",LC π filter at M.2 Key-E (< 20 mVpp)
34P-09,VBAT (05 §4) / VSYS (09 §5.1) — conflict,"3.3 V AON LDO (TPS7A16, 100–150 mA)",VBAT or VSYS,≤ 120 mA,Verified,"05 §4, §5, 09 §5.1",05 feeds the AON LDO from VBAT (pack); 09 feeds it from VSYS. Drawn from VBAT (keeps EC alive with charger in ship mode); reconcile at schematic
35P-10,3.3 V AON,"nRF5340 EC, Hall, RTC, SMBus pull-ups, LED bar (if ≤ 100 mA)",3.3 V AON,≤ 120 mA,Verified,"05 §3.2, §11",Coin cell MS621 (3 mAh) backs the RTC
36P-11,5.0 V SYS,SoM VIN via J1/J2,5.0 V ±3 %,≤ 1.6 A (8 W peak),Verified,05 §3.2,SoM's RK806 PMIC generates its own rails
37P-12,5.0 V SYS,"Port A source eFuse 1.5 A → J4 VBUS (source role, PR_Swap phone top-up)",5.0 V,1.5 A,Verified,"05 §4, §7.2",
38P-13,5.0 V SYS,"OLED VCC boost 12 V (TPS61041 class, or in module) → J10",12 V,~30 mA,Verified,"05 §4, §5",
39P-14,5.0 V PORT B,"TPS2596 eFuse (3.3 A trip, EC ILIM 0.5/1.5/3 A) → J5 VBUS",5.0 V,0.5 / 1.5 / 3 A,Verified,05 §7.4,Reverse-current blocking; VBUS applied only after Rp is set
40P-15,3.3 V SLOTS,J3 mezzanine pins 44–51 (8 pins) → RB slot eFuses,3.3 V,"≥ 6 A total, 0.75 A/pin derated",Verified,09 §8.1,
41P-16,3.3 V SLOTS,eFuse 2.5 A (Pro) → J9 M.2 NVMe 3.3 V,3.3 V,≤ 1.8 A,Verified,"05 §3.2, §4",Alternative: separate 3 A buck — EVT decision
42P-17,RB 3.3 V slots (post-mezzanine),5× eFuse TPS2596 class → slots J1–J5,3.3 V,"CFe B 2.5 / CFe A 1.5 / CFast 1.0 / SD 0.8 / µSD 0.5 A (09 §5.2) vs 2.0 / 1.2 / 1.2 / 0.5 / 0.3 A (05 §3.2, §4) — conflict",Verified,"09 §5.2, 05 §3.2",EN = PWR_EN from EC AND card-detect; soft-start 1–2 ms; active discharge on CFe B; fault wired-OR to SLOT_FAULT#
43P-18,3.3 V LOGIC,ASM2812 I/O + 1.05 V local buck (TPS62823),3.3 V / 1.05 V,~1 A core,Verified,"05 §4, 09 §5.1",Point-of-load buck ≤ 15 mm from the chip
44P-19,3.3 V LOGIC,RTL8126 I/O + 1.05 V local buck,3.3 V / 1.05 V,≤ 1.5 A core,Verified,"05 §4, 09 §5.1",
45P-20,3.3 V LOGIC,ASM3142 + 1.05 V local buck,3.3 V / 1.05 V,—,Verified,"05 §4, 09 §5.1",
46P-21,3.3 V LOGIC,Load switch (ASM2464_PWR_EN from EC) → ASM2464PD + 1.05 V local buck + SPI flash (Pro),3.3 V / 1.05 V,~1.2 A core,Verified,"05 §7.5, 09 §5.1, 02 §6.1",Bridge unpowered in standalone mode (zero draw)
47P-22,3.3 V LOGIC,J8 M.2 Key-E (MT7925) via LC π filter,3.3 V,≤ 0.75 A (2.5 W pk),Verified,05 §5,
48P-23,3.3 V LOGIC,"PI3DBS16412 lane mux, HCSL clock mux, 74LVC1G373 latch, TPM SLB9672 (1.8 V I/O per 09 §5.1), PD controllers ×3",3.3 V,small,Verified,"05 §4, 09 §5.1, §5.4",
49P-24,3.3 V LOGIC,J3 mezzanine pins 52–53 → RB GL9755 / GL9750 / ASM1064 (+ RB 1.2 V ASM1064 core),3.3 V,~0.4 A,Verified,"09 §8.1, §2.2",
50P-25,"1.8 V buck (1 A) on MB, fed from 3.3 V LOGIC (05 §3.2)","UHS-II I/O (via mezzanine pin 54), TPM, misc I/O",1.8 V,0.6 A,Verified,"09 §5.1, §8.1","05 §5 lists a TLV75518 LDO for the readers' 1.8 V — one 1.8 V source, two documents; reconcile"