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# PoppyUp — Prototype Roadmap: PoC → EVT → DVT → PVT → MP **Document:** 13-roadmap.md · **Baseline:** ADR v0.3, 2026-09-27 (owner review D1–D13: magnesium chassis, desk-operation assumption, Port C Pro-only and decoupled from Base, SoM bake-off, ODM engaged, fan gate at EVT exit) · **Derives from:** `00-architecture-decisions.md` §12; verification stages referenced by `01-requirements.md`. Certification detail lives in `11-certification.md`; risks in `12-risks-open-questions.md` (v0.3 numbering). ## 0. Timeline at a glance (month 0 = program start, assumed October 2026) | Stage | Months | Calendar (assumed) | Units | Purpose in one line ||---|---|---|---|---|| **PoC** | 0–2 | Oct–Dec 2026 | 3 dev-kit rigs (one per SoC path) | Retire the architecture-level risks with off-the-shelf boards before drawing a schematic; **decide SoM vs board-down at exit**. || **EVT** | 3–7 | Jan–May 2027 | 15–20 | First custom PCBs in a machined magnesium enclosure; prove electrical, thermal, RF, and mode-switching at the board level; **fan gate at exit**. || **DVT** | 7–12 | May–Oct 2027 | 60–100 | Near-final tooling (Mg soft tool); prove drop, ingress, life, regulatory pre-compliance; enter formal FCC/ISED/CE testing. || **PVT** | 12–15 | Oct 2027–Jan 2028 | 200–500 | Production tooling (AZ91D die-cast) and line at the ODM; yield, test coverage, final certifications, packaging. || **MP** | 15+ | Jan 2028 → | ramp | Ship Base; Pro follows when the Port C track is done. | Total to first shipment ≈ 15 months — **unchanged in v0.3**. The critical path in the second half is hard tooling (magnesium die-cast chassis, PC frame) and DVT verification, not carrier certification — with no built-in modem (ADR §14, confirmed final by D1) there is no PTCRB → carrier chain, and the FCC/ISED/CE grants land ~2 months after DVT samples without gating MP. **Gates added in v0.3 (ADR §12):**- **PoC exit (month 2) — SoM / board-down decision (D12):** Firefly Core-3588J vs Forlinx FET3588-C vs board-down RK3588J on the ODM's reference design, scored against the ADR §3.1 criteria (§1.2a below).- **ODM design review (month 2–3) — before EVT schematic kick-off (D12):** the design-review package in §2.0; the ODM's answers shape EVT-A.- **EVT exit (month 7) — fan gate (D5):** passive for EVT; pass/fail criteria in §2.5 on AZ91D-corrected magnesium thermal data, shutter closed and open; any fail designs the sealed tunnel fan into DVT.- **Base launch decoupled from Port C (D7):** Port C / ASM2464PD validation is a parallel Pro track (§2.7) that may slip to a later Pro revision without moving the Base date. ```mermaidgantt title PoppyUp hardware program (months from start) dateFormat YYYY-MM axisFormat %b %y section Engineering PoC dev-kit rigs (3, SoM bake-off) :poc, 2026-10, 2026-12 SoM / board-down decision :milestone, g1, 2026-12, 0d ODM design-review package + review :odm, 2026-12, 2027-01 EVT design + fab (main, reader, pack) :evt_d, 2026-12, 2027-02 EVT build + test (15-20, machined Mg) :evt, 2027-02, 2027-05 EVT-exit fan gate :milestone, g2, 2027-05, 0d DVT design + Mg soft tooling :dvt_d, 2027-04, 2027-06 DVT build + test (60-100) :dvt, 2027-06, 2027-10 PVT hard tooling + line (ODM) :pvt_d, 2027-09, 2027-11 PVT build (200-500, AZ91D castings) :pvt, 2027-11, 2028-01 MP ramp (Base) :mp, 2028-01, 2028-04 section Pro track (Port C, may slip - D7) Port C / ASM2464PD validation :pro1, 2027-02, 2027-10 Pro FCT fixture + regulatory addendum :pro2, 2027-09, 2027-12 Pro population release :milestone, g3, 2028-01, 0d section Firmware (Phase 2, needed by HW) Bring-up firmware (DT, drivers, EC) :fw1, 2027-01, 2027-05 Job engine + connectors alpha :fw2, 2027-04, 2027-09 iPhone app alpha :fw3, 2027-06, 2027-11 Beta firmware/app :fw4, 2027-10, 2028-01 section Certification Pre-compliance scans (EVT) :pc1, 2027-04, 2027-05 Pre-compliance full (DVT) :pc2, 2027-08, 2027-09 UN 38.3 + IEC 62133-2 (pack) :bat, 2027-06, 2027-09 MIL-STD-810H drop, IP54 lab :env, 2027-08, 2027-10 FCC / ISED / CE RED formal (DVT-1 units, Base) :reg, 2027-08, 2027-11 UL/IEC 62368-1 :ul, 2027-10, 2028-01 PVT drop/IP re-test on castings (mandatory) :pvtenv, 2027-12, 2028-01 section Long-lead Mg die-cast chassis tool (hot-chamber) :tool1, 2027-07, 2027-11 Mg coating supplier qualification :coat, 2027-03, 2027-07 PC frame + TPU overmold tooling :tool2, 2027-07, 2027-10 Shutter mechanism tooling :tool3, 2027-07, 2027-10 SoM / board-down volume allocation :ll1, 2027-06, 2027-12``` --- ## 1. PoC — Proof of Concept on development kits (months 0–2) ### 1.1 GoalsAnswer, with measurements, the questions that decide whether the ADR topology survives — before any custom PCB exists — and **choose the SoC carrier form** (SoM vs board-down, D12). No enclosure, no app, no job engine. ### 1.2 Hardware: three bench rigs (identical peripherals, one SoC platform each — the SoM bake-off) The three rigs already exist in the plan; v0.3 assigns one SoC path to each so the bake-off runs in parallel with the peripheral tests. | Rig element | Part | Purpose ||---|---|---|| SoC platform — **Rig 1** | **Firefly Core-3588J** on Firefly's carrier (or ITX-3588J: full RK3588, PCIe ×4 slot + M.2, both USB3 OTG exposed) | SoM path 1 (v0.2 default) || SoC platform — **Rig 2** | **Forlinx FET3588-C** on the Forlinx OK3588-C carrier | SoM path 2 (pin-incompatible with Firefly; carrier respin ~3 weeks if chosen) || SoC platform — **Rig 3** | **Board-down RK3588J**: the ODM's RK3588 reference / evaluation board, or the Rockchip RK3588 EVB as the equivalent if the ODM has no board of its own | Board-down path; also the audit vehicle for the ODM's reference design quality (R9) || — all rigs | Mainline-based Linux (6.12 LTS or newer); `pcie3x4`/`pcie3x2` bifurcation test and dwc3 gadget on each platform | Bake-off criteria §1.2a || CFexpress B path | PCIe ×4 slot → **×2 riser → PI3DBS16412 evaluation board → M.2-to-CFexpress Type B adapter** (commercial "CFexpress B to M.2 M-key" adapters) | Gen3 ×2 read test; hot re-route test || USB4 bridge | **ASM2464PD** USB4 NVMe enclosure PCB (Acasis/ORICO-class, bare board) with its M.2 socket fed from the mux "B" side via a short M.2 extender | Path 1 to Mac and iPhone; measure ~3 GB/s and ~900 MB/s; RO configuration check (P14) || Switch fabric | **ASM2812 quad-M.2 riser** (commercial ×4→4× M.2 card) in the board's second slot or via bifurcated riser | Concurrency, enumeration, ASPM behaviour, power draw || Ethernet | **RTL8126 5GbE M.2/PCIe card** on the ASM2812 riser; peer: a 5GbE-capable switch + MinIO on a workstation | NFR-010 || Tethering | iPhone 15/16/17 (USB-C) + a Pixel and a Galaxy + one USB LTE/5G adapter (e.g. a Quectel/Fibocom-based retail dongle, or a Netgear/TP-Link hotspot in USB-NCM mode) on the ASM3142 USB 3.2 host card | Enumeration (`ipheth`, `cdc_ncm`/`rndis_host`, `cdc_mbim`/`qmi_wwan`), uplink vs the phone's own speed test, current draw at the 0.5/1.5/3 A charge settings, attach/detach cycling || Wi-Fi | **MT7925 M.2 E-key module** (AzureWave AW-XB591NF) + 2 antennas | STA+AP concurrency, throughput, power || SD / microSD / CFast | GL9755 PCIe SD reader card; GL9750-based microSD; **ASM1064** SATA card + SATA-to-CFast adapter | NFR-014 rates; trained link width || USB host | **ASM3142** PCIe USB 3.2 Gen2 card + Samsung T9 (shared with the tethering tests — Port B is one receptacle) | SSD ingest rate || NVMe | WD SN770 1 TB in ASM2812 riser slot | Quick-copy path; sustained write || EC stand-in | **nRF5340-DK** wired to mux SEL, PERST#, slot power switch, Hall sensor, OLED breakout (SSD1309), fuel-gauge EVM | Sequencing logic, BLE provisioning demo (incl. the Job Location GATT write), OLED || Power | **BQ25792 EVM** + **TPS25750 EVM ×2** (Port A sink, Port C sink) + **TPS2121 EVM** (VBUS priority mux) + **BQ40Z50-R2 EVM** + bench 2S2P pack of 4 × Samsung 50E in a holder | Charge/discharge curves, PD negotiation with 5 chargers + MacBook, hot-unplug behaviour, Port C ⇄ Port A VBUS OR-ing (D7) || Instrumentation | Joulescope or Otii Arc (power), Keysight/Rigol scope (≥ 1 GHz for control signals only), thermocouples, reference iPhone 15 Pro + iPhone 15, M-series Mac, TB4 Windows laptop | | Rig cost ≈ $4–5 k each; three rigs ≈ $14 k (the Forlinx kit and the RK3588 EVB / ODM board add ~$1–2 k over the v0.2 all-Firefly plan) plus cards (~$3 k for a representative card library from Sony/ProGrade/Lexar/Angelbird/Delkin/SanDisk/Nikon incl. CFast — no XQD, D10) and network peers (~$2 k). ### 1.2a SoM / board-down bake-off — scored at PoC exit (D12, ADR §3.1) Score each criterion 0–3 per platform; weights reflect how hard the item is to fix later. "Decide at PoC exit" — the winner sets the EVT-A schematic; the runner-up SoM stays as the documented fallback pinmap until EVT-B. | # | Criterion (ADR §3.1) | Weight | Firefly Core-3588J | Forlinx FET3588-C | Board-down RK3588J (ODM ref.) | Evidence ||---|---|---|---|---|---|---|| C1 | `pcie3x4` ×2+×2 bifurcation and exposure of all 7 PCIe lanes on the carrier | 3 | | | | P1, P6 on each rig; pinmap review || C2 | Both USB3 OTG ports with dwc3 gadget (UAS/BOT to iOS/macOS) | 3 | | | | P4 on each rig || C3 | Thermal interface: SoC top height, boss geometry, measured ΔT at 8 W into a bench plate | 2 | | | | Thermocouple on each rig at 8 W || C4 | Longevity / EOL terms in writing (≥ 5 years), lifecycle letter | 3 | | | | Vendor letters (SoMs); RK3588J longevity + ODM DDR/PMIC sourcing (board-down) || C5 | Price at 1 k / 10 k (SoM price, or board-down BOM adder + ODM layout/boot-firmware NRE amortised) | 2 | | | | Quotes || C6 | Second-source / pin-compatibility story | 2 | | | | Firefly ↔ Forlinx are pin-incompatible; board-down has none but removes the SoM vendor || C7 | ODM's ability to support the path (layout, boot firmware, DDR sign-off, test) | 2 | | | | ODM design review (§2.0) || | **Weighted total (max 51)** | | | | | **Decide at PoC exit** | Board-down is only eligible if the ODM's reference design passes a schematic/DDR/boot-firmware audit at PoC (R9); otherwise the decision is between the two SoMs. ### 1.3 What is validated (pass criteria in `01-requirements.md` / `03-datapath-bottlenecks.md` §6) | # | Test | Retires ||---|---|---|| P1 | RK3588 `pcie3x4` bifurcates ×2+×2 on each bake-off platform; CFe B 4.0 cards from 3 vendors train Gen3 ×2 and read ≥ 1.6 GB/s (M1) | Assumption A7/A8; bake-off C1 || P2 | Hot re-route CFe B between SoC root and ASM2464PD via PI3DBS16412 + REFCLK mux, scripted PERST#/power sequencing from nRF5340-DK: 1 000 cycles, 0 training failures, card FS clean (M3) | Mode-switch architecture (R1; Pro track) || P3 | ASM2464PD to M-series Mac ≥ 2.8 GB/s; to iPhone 15 Pro ≥ 900 MB/s via UAS fallback; Files app browses exFAT (M2) | Path 1 value || P4 | dwc3 `f_tcm` UAS and `f_mass_storage` BOT gadgets to Mac/Win/iPhone 15 Pro/iPhone 15 on each bake-off platform: rate ≥ 380 MB/s (USB3) and ≥ 38 MB/s (USB2), read-only LUN enforced (SCSI WP bit; macOS must not write `.Spotlight-V100`/`.fseventsd`), composite with CDC-NCM works driverless (M5) | Path 2 value; iOS UAS support (confirm or fall back to BOT); bake-off C2 || P5 | S3 (MinIO) over RTL8126 5GbE with TLS 1.3 + SHA-256 + xxHash64 using a throwaway multipart uploader (Go or Rust, 16 parts): ≥ 480 MB/s at ≤ 2 A76 cores (M4) | CPU/crypto budget || P6 | ASM2812: enumeration, ASPM L1 power, concurrency fairness (M6); measure switch power idle/active | Switch choice vs PEX8724 fallback || P7 | USB tethering on the ASM3142 host: iPhone 15/16/17 and Pixel/Galaxy enumerate ≤ 10 s after the trust prompt; uplink ≥ 90 % of the phone's own speed test at 5 sites; 100 attach/detach cycles with the job engine stand-in resuming; Port B charge-current control at 0.5/1.5/3 A verified with a USB power meter, and the 3 A setting refused by the EC stand-in unless a PD source is present (D13); one USB LTE/5G adapter over MBIM/QMI or NCM (M7) | Tethered-uplink mode (ADR §4.3), tethering stack maturity (R4/R14), Port B power sizing and policy || P8 | MT7925 STA+AP concurrent ≥ 60 % of STA-only; AP visible to iPhone; power (M8) | Management-transport plan || P9 | GL9755 HD312 ≥ 280 MB/s; GL9750 ≥ 90 MB/s; ASM1064 + CFast ≥ 480 MB/s and record trained link (M9); a non-NVMe PCIe device in the CFe B path is rejected cleanly with the "XQD not supported" message and no damage (any non-NVMe M.2 PCIe device via the adapter — the only XQD behaviour kept, D10) | Slot controller choices || P10 | Power: BQ25792 NVDC hot-unplug at 15 W load ×100, no reset; charge curve 0→80 % ≤ 1.7 h at 65 W; PD sink 0 mA from iPhone; PR_Swap source 5 V to iPhone; **Port C PD sink (D7, Pro): TPS2121 ORing Port C VBUS (Mac 15 W, then a 65 W PD source) with Port A, Port A priority, break-before-make, no charger input glitch on either transition** | Power-tree architecture incl. the Pro Port C input || P11 | Component power table (ADR §6.1) measured for every item; mode budgets (ADR §6.2) recomputed | Runtime claims || P12 | Read-only integrity: `dd` image before/after 10 mount/upload/unmount cycles incl. dirty-bit exFAT — identical | FR-003 || P13 | **NWPC survey (D8):** `nvme id-ctrl` on every card in the library — record Identify Controller byte 531 (NWPC) and whether Set Features 0x84 state 1 (Write Protect) is accepted and persists across the slot power cycle used by the mode switch; then confirm a Mac (native USB4) and an iPhone (UAS) mount the protected namespace read-only | Port C read-only mechanism (R2); sizes the consent-fallback population || P14 | **ASM2464PD read-only configuration check (D8):** with the owner's ASMedia-access team, determine whether the bridge firmware/tool exposes a SCSI WP / read-only configuration in UAS/BOT mode; confirm it has no effect in native USB4 mode | Port C read-only mechanism (R2); ASMedia access (R15) || P15 | **SoM / board-down bake-off (D12):** §1.2a scoring table completed with measured C1–C3 and documented C4–C7 | Q11 (SoM), R10 | ### 1.4 Firmware scope at PoCYocto/Buildroot image on mainline-tracking kernel with Rockchip patches, built for each bake-off platform; device-tree for the bifurcated PCIe; shell/Python test harness incl. the `nvme-cli` NWPC survey script; throwaway multipart uploader; nRF5340-DK Zephyr app for sequencing + BLE demo (status/provisioning + Job Location GATT characteristic) + OLED. No job engine, no persistence, no app. ### 1.5 Exit criteriaP1–P5 pass; P6–P14 pass or have an approved fallback (e.g., PEX8724 lane plan, BOT instead of UAS, consent-fallback as the Port C RO baseline). **SoM / board-down decision made (P15, Q11)** and the EVT-A schematic kicked off on the winner after the ODM design review (§2.0). ASM2812 vs PEX8724 posture confirmed with the ASMedia team. Updated ADR v0.4 with measured numbers. (5GbE vs 10GbE is decided — D6 — and Port C's SKU placement is decided — D7 — so neither is an exit item any more.) ### 1.6 Cost / time≈ $20 k hardware (the extra SoC kits fit inside the rig budget), 2 engineers × 2 months (+ 1 firmware engineer part-time). Deliverables: PoC test report incl. the bake-off scorecard and the NWPC card survey, ADR v0.4, ODM design-review package (§2.0), EVT schematic kick-off. --- ## 2. EVT — Engineering Validation Test (months 3–7) ### 2.0 ODM design-review package — before EVT schematic kick-off (D12) The ODM/CM is engaged from the start of EVT rather than at DVT DFM. Before the EVT-A schematic is started we hand them a review package and get written answers; the review is a gate (§0), not a courtesy. **Package contents:** the ADR (v0.4 with PoC numbers); system block diagram (`02`); component selection with alternates (`04`); PCB architecture — stackup, board set, mezzanine, high-speed rules (`09`); mechanical concept — magnesium chassis, PC frame, TPU, shutter, coating stack, galvanic rules (`08`); BOM at 1 k / 10 k (`10`); the PoC test report and bake-off scorecard. **Question list for the ODM:**1. Preferred / approved-vendor parts for every line where we chose freely (bucks, eFuses, connectors, passives); alternates they already stock.2. DFM/DFT feedback on the 10-layer hybrid stackup, back-drilling, the 0.635 mm mezzanine, test-point strategy and ICT/FCT coverage; their capability for Megtron 6 / I-Speed hybrid boards.3. Test capability: high-speed loopback (Gen3/Gen4/USB4), RF calibration (Wi-Fi TRP), IP leak test, shutter-force gauging, cycle time target ≤ 6 min/unit.4. **Magnesium die-cast and coating suppliers:** hot-chamber AZ91D casting partner, chromate-free conversion coat + powder/e-coat line with masking capability, thixomold or T0 soft-tool option for DVT, and coupon test support (500 h salt fog, contact resistance).5. **Battery-pack vendor** with UN 38.3 / IEC 62133-2 experience and the BQ40Z50-R2 pack PCB.6. **RK3588 board-down reference design:** do they have one (schematic, DDR sign-off, PMIC, boot firmware, mass-production history)? Under what terms? This feeds bake-off criterion C7 and the eligibility test in §1.2a.7. Tooling ownership, design-file escrow, NRE schedule, exit rights (R9). **Who owns what from EVT onward (keep generic; contract sets the detail):** | ODM / CM | Us ||---|---|| Layout and DFM review (from EVT-B), fab and assembly, FCT/ICT fixture design and build (Base fixture first, Pro fixture on the Pro track), line NRE, hard tooling from DVT exit, magnesium die-cast + coating supplier management, battery-pack vendor management, packaging, ORT | Architecture and ADR, schematics and EVT-A layout, firmware (SoC, EC, factory test scripts), verification (EVT/DVT test plans and reports), compliance (labs, filings, technical files), industrial design and shutter mechanism | ### 2.1 GoalsFirst custom PCB set in a **machined AZ31B magnesium chassis (or thixomolded AZ91D if the ODM's casting partner offers it faster or cheaper) — not CNC aluminum (D4)** — with a 3D-printed PC frame stand-in. Prove the design electrically and thermally; validate RF with real antennas in the real geometry; run every mode-switch and power scenario on the intended silicon; give firmware a stable platform; **produce the thermal data the fan gate is called on (§2.5)**. ### 2.2 Hardware built | Item | EVT specification ||---|---|| Main board | 10-layer hybrid stackup per `09-pcb-architecture.md`; SoM connectors or board-down SoC per the PoC-exit decision; Port C parts (ASM2464PD, third TPS25750, TPS2121-class mux) populated on the Pro-track units only; **two fab spins budgeted** (EVT-A months 3–4, EVT-B months 5–6; EVT-B layout with the ODM) || Reader daughterboard | 8-layer; two variants: full 5-slot and no-CFast (validates FR-093) || Battery pack | Hand-built 2S2P with production-intent pack PCB (BQ40Z50-R2, BQ294xx), non-UN38.3-certified (bench/lab use only, ground shipping) || Enclosure | **Machined AZ31B magnesium chassis (or thixomolded AZ91D), chromate-free conversion coat + 40–60 µm matte grey powder/e-coat with the gap-pad bosses and EMI-gasket lands masked bare-conversion as in production; Zn-Ni / Al fasteners and inserts per ADR §8** + SLA/MJF PC frame + machined shutter slats (hard-anodized 6061) with production-intent POM rails/detents/seal grooves; TPU bumpers cast in silicone moulds; 5 sets. Plus **coated AZ91D coupons** (with fasteners, inserts, gasket land) for the corrosion tests || Antennas | Flex antennas (dual-band/tri-band Wi-Fi ×2) on the final front-frame positions; BLE chip antenna on the EC; antenna house iterates matching || Display / LEDs | Production SSD1309 OLED module + LED bar flex || Quantity | 15–20 board sets; 5 fully assembled units (3 Base population, 2 Pro population), 10 board-only bench units || Test fixtures | Bed-of-nails not yet (ODM starts fixture design from EVT-B); JTAG/UART/SWD headers populated; 4 automated card insert/remove cyclers built (pneumatic) for SAF-050 / FR-043 | ### 2.3 What is validated | Area | Tests (requirement IDs) | Pass ||---|---|---|| Signal integrity | Eye/BER on CFe B Gen3 ×2 both mux paths, Gen4 ×2 mux-to-ASM2464PD, USB4 20 GBd lanes (Pro units), ASM2812 ports, mezzanine (FR-093) | Compliance masks with ≥ 20 % margin; PCIe LTSSM logs clean over 24 h soak || Mode switching | FR-040…045 on real board: 1 000 attach/detach cycles per port with live uploads, timing ≤ 5 s / ≤ 8 s; Port C RO path per ADR §4.2 (NWPC set-before-switch on supporting cards; consent prompt on the others) | 0 FS errors, timing met; RO/consent behaviour as specified (Pro track) || Card compatibility | IF-001…006 card matrix (≥ 25 cards; NWPC flag recorded per card) | All mount, rates per NFR-014 || Host compatibility | FR-041/042/046 on Mac (M1/M2/M3/M4), Intel TB4 PC, AMD USB4 PC, Windows 11, iPhone 15/15 Pro/16 Pro/17 Pro, iPad Pro M4; hosts mount Port A LUNs read-only; writes only after the app toggle (D8) | Driverless enumeration ≤ 5 s; no host-side writes in RO || Power | NFR-022 rail transients with CFe 5 W peaks and Port B 3 A tether load steps; NFR-023 charge; NFR-024 efficiency; SAF-070 hot-unplug; FR-076 standby ≤ 0.12 W; ADR §6.2 mode budgets re-measured; **Port B 3 A only with PD present (D13, EC-enforced); Port C PD sink OR-ing on Pro units (D7)** | Within ADR ± 10 %; policies enforced || Thermal | NFR-030…034 with thermocouple map in the machined Mg chassis, **shutter closed AND open** (parked slats over the top band of the rear face); throttle policy NFR-032 and the **thermal safety rule (D2: 52 °C skin / 60 °C air → checkpoint → standby → auto-resume at 42/45 °C)** exercised in chamber at 25/35/45 °C; **all AZ31B results corrected ~30 % for AZ91D conductivity (ADR §8) before use in §2.5** | Skin ≤ 48/55 °C; policy stable; corrected data set delivered to the fan gate || Coating / galvanic (new, D4) | Coupons: 500 h neutral salt fog (ASTM B117, verify) on the coating stack with Zn-Ni and Al fasteners, inserts and the masked EMI-gasket land; gasket contact resistance before/after; cross-hatch adhesion; thermal cycling −20…+60 °C; boss-face bare-conversion pad thermal resistance vs a powder-coated control | No red rust/white corrosion beyond spec at fastener sites; contact resistance stable; adhesion class ≤ 1 || RF | Wi-Fi only: passive antenna efficiency in the coated Mg enclosure (IF-012), conducted power/sensitivity at the MT7925 module connectors, radiated pre-scan on a 3-D chamber, coexistence SAF-060 (1 TB read under max Wi-Fi TX) | Efficiency targets; 0 read errors || EMC pre-scan | Radiated/conducted emissions (Base population; Pro units separately on the Pro track), ESD ENV-013; EMI gasket on masked lands | Margin ≥ 6 dB before DVT || Mechanical (pre) | Shutter force/detent feel, ENV-010 recess gauge, connector anchoring ENV-011 40 N side-load; mass of the assembled unit vs ~828 g budget (AZ31B ≈ 830–840 g expected) | Pass on machined parts; mass within budget || Modularity | FR-090/091: MT7925 and QCNCM865 Wi-Fi modules both enumerate (Key-E alternates); FR-092 NVMe socket empty vs fitted; Port C feature flag off = Base behaviour on a Pro board | Pass || Secure boot chain | SAF-010/011/012 on unfused parts (keys in test OTP emulation), TPM sealing, RAUC A/B (FR-064) | Pass on dev keys | ### 2.4 Firmware scope at EVTBring-up image with full device tree for the main board; EC firmware v0 (sequencing, gauge, thermal ladder + thermal safety rule, Port B PD-present policy, OLED, BLE GATT status/provisioning + Job Location); job-engine skeleton with persistence to exercise FR-004/070/071 (S3 and SFTP only); Port C path behind a feature flag (default off on Base); factory test scripts for every interface. Still no app — an engineering CLI/web page over NCM/Wi-Fi substitutes. ### 2.5 EVT-exit fan gate (D5) **Inputs:** the §2.3 thermal data on machined AZ31B (corrected to AZ91D, or measured on thixomolded AZ91D units), desk, free air, shutter closed **and** open, 25 / 30 / 35 °C ambient. **Pass = all of:** | | Criterion | Model prediction (`06-thermal.md`, ADR §6.2) ||---|---|---|| (a) | One 512 GB 5GbE upload (~15 min at ~500 MB/s) completes without throttling at 25 °C, and runs ≥ 8 min before throttling at 35 °C | Pass (~17 min from 25 °C, ~9 min from 35 °C) || (b) | Wi-Fi upload at 80 MB/s **and** USB4 reader mode (Pro) each run ≥ 60 min at 25 °C without throttling | **Marginal** (ceilings 25 / 24 °C and 25 / 23 °C closed / open) || (c) | Hotspot / USB-tether upload runs indefinitely at 30 °C | Pass (ceiling 30 / 29 °C) || (d) | Skin ≤ 48 °C on metal / ≤ 55 °C on plastic throughout all of the above | Pass by construction of the throttle ladder — verified, not assumed | **Decision rule:** all four pass on corrected data → passive design confirmed; the tunnel-fan envelope stays reserved but empty through DVT/PVT. **Any fail → the sealed tunnel fan is designed into DVT** (fan, duct, sealed inlet/outlet membranes, EC fan control, +noise/+power/+cost captured in `10-bom.md`), with DVT thermal units built in AZ91D. If (b) alone fails by a small margin, the owner may accept "throttles on a warm desk" for Wi-Fi/USB4 instead — that acceptance is recorded in the ADR, not assumed. The gate is called on the AZ91D-corrected numbers only; an uncorrected AZ31B pass does not count (R8). ### 2.6 Exit criteriaAll P0 EVT-stage requirements pass or have a DVT-scheduled fix; EVT-B board is DVT-intent (only layout tweaks remain); BOM at 1 k volume quoted by the ODM within 10 % of `10-bom.md`; ADR v0.5; industrial design frozen for tooling; **fan gate called (§2.5)**; coupon results in (R7); ASM2812 confirmed or PEX8724 fallback invoked (EVT freeze, R15); **decision to release the Mg thixomold/soft tool and PC injection soft tool** (long lead). Base-track items gate EVT exit; Pro-track items (§2.7) do not. ### 2.7 Base launch decoupled from Port C (D7) Port C / ASM2464PD is a **parallel Pro track**, not a Base dependency: - **Firmware feature flag:** the Port C path (mux control, ASM2464PD power, NWPC/consent flow) is compiled in but disabled on Base; Base ships and is validated with the flag off, and a Pro board with the flag off must behave identically to Base (§2.3 Modularity).- **Separate Pro FCT fixture:** the Base FCT fixture does not exercise Port C; the ODM builds a Pro fixture (USB4 loopback, PD-sink test, mux cycling) on the Pro-track schedule.- **Pro regulatory addendum:** Base FCC/ISED/CE testing covers the Base population; the Pro population gets a 15B SDoC addendum, RED technical-file update and a 62368-1 variation for the Port C power input (`11-certification.md` §1a, ~$8–15 k, verify).- **Rule:** a slip on any Port C item (R1, R2, R11 USB4 SI, ASM2464PD firmware, Pro fixture, Pro addendum) **moves the Pro SKU date, never the Base date**. Base exit criteria at every stage are written on the Base population; Pro-track items are tracked on their own line in the Gantt. ### 2.8 Risks retired / costRetires: SI at Gen4/USB4 with the mux (Pro track); power-tree peak handling incl. the Port C OR-ing; thermal envelope (fan gate); RF windows in the coated Mg enclosure; SoC carrier pinout/bifurcation; coating/galvanic stack (coupons). Cost ≈ **$120–160 k** (two PCB spins incl. NRE ~$40 k, **machined-magnesium/SLA enclosures ~$35 k** (was ~$25 k CNC aluminum) incl. coating and coupons, antenna house ~$12 k, components/modules ~$25 k, chamber time ~$15 k). Team: 2 EE, 1 ME, 0.5 RF (contract, part-time — Wi-Fi/BLE only), 2 FW, 0.5 PM, plus ODM engineering liaison. --- ## 3. DVT — Design Validation Test (months 7–12) ### 3.1 GoalsProve the *product* — not the board — against every environmental, life, safety and regulatory requirement, on units built with near-final materials and processes (magnesium AZ91D from a soft tool), and enter formal regulatory testing on the Base population. ### 3.2 Hardware built | Item | DVT specification ||---|---|| PCBs | DVT layout (EVT-B + fixes) by the ODM; production stackup and fab vendor; ICT/FCT test points added; 60–100 sets || Enclosure | **Magnesium soft tooling: thixomolded or T0 (first-shot, soft/prototype tool) AZ91D chassis (~$35 k, verify) with the production coating stack and masking** — thermal/environmental units in AZ91D so the fan decision and drop data reflect production material; if the soft tool slips, machined AZ31B for the non-thermal units only, flagged as such; production PC+GF injection soft tool, TPU overmold soft tool, stamped/anodized shutter slats, moulded silicone seals, POM rails; if the fan gate failed, sealed tunnel fan + ducts on all units || Antennas | Flex antennas final; **LDS-on-PC trial** on 10 units to de-risk the volume transition || Battery | Production-intent pack from the ODM-managed pack vendor with UN 38.3 and IEC 62133-2 testing started on 10 packs || Quantity | 60–100 units: 30 environmental/reliability, 15 regulatory (Base population), 25 firmware/app/alpha users, rest spares; Pro population on ~10 units for the Pro track || Fixtures | **ODM-owned:** bed-of-nails ICT, Base functional test station v1 (Pro station on the Pro track), shutter cycler; drop fixture rented at lab | ### 3.3 What is validated | Area | Tests | Pass ||---|---|---|| Drop | ENV-003 MIL-STD-810H 516.8 Proc. IV, 5 units, 26 drops each, operating with cards. **Note (D4):** results on machined AZ31B (ductile) do not transfer to die-cast AZ91D (~3 % elongation, porosity) — DVT drop units must be AZ91D soft-tool shots, and the PVT repeat on production castings is mandatory (§4.3) | Functional after; 0 card data loss || Ingress | ENV-004 IP54 shutter closed; IP52 open; receptacle IP67 sample tests | Pass at accredited lab || Climate | ENV-005 chamber matrix in each mode (desk, free air, shutter open and closed); ENV-006 humidity; ENV-008 altitude vent | Pass || Thermal safety rule (replaces the v0.2 in-bag test, D2) | Device packed away mid-job (insulated box, shutter closed, all links up): job engine checkpoints at 52 °C skin / 60 °C air, slots and radios off, OLED "Too hot — paused, will resume", BLE notification; auto-resume at ≤ 42 / 45 °C with cards and link present; no data loss; 48 °C mechanical switch never reached first | State machine per `02-system-architecture.md` §7; resume verified 10× || Corrosion / galvanic (D4) | Coated AZ91D castings (not coupons): 500 h neutral salt fog on 3 units with fasteners and gaskets; disassembly inspection of inserts, detent housings, gasket lands, shutter-track interface; contact resistance re-check | No functional corrosion; shielding contact intact || Vibration | ENV-007 514.8 Cat 4 with cards | No errors || Life | NFR-040 shutter 10 k cycles ×3 units; NFR-041 connector 1 k sample; NFR-042 | Pass || Battery | REG-004 UN 38.3 T1–T8; IEC 62133-2; SAF-040 protections; NFR-021 runtime per mode on 5 units | Certified; runtime ≥ targets || Thermal (final) | NFR-030…034 on AZ91D soft-tool castings + PC parts (production conductivity, porosity and emissivity; confirms the EVT correction, R8), shutter open and closed; fan variant if designed in | Pass; EVT correction within ±10 % || Regulatory pre-compliance | Full FCC 15B/15C, RED radio + EMC, Wi-Fi SAR pre-scan at intended body positions on the Base population; results drive antenna/power-table tuning; formal FCC/ISED/CE submissions follow on DVT-1 units (`11-certification.md` §11); Pro population pre-scanned on the Pro track | ≥ 3 dB margin || Safety | SAF-041 62368-1 pre-assessment (Base; Port C power input as a variation on the Pro track); SAF-050 10 k insert cycles | Pass || Firmware/system | FR-001…011 job engine incl. all four endpoint types; FR-020…029 links and failover; FR-060…064 management with **app alpha** incl. Job Location over BLE/NCM and the Port C consent prompt (Pro); FR-070…076 power; UX-010…050 usability with 10 target users | P0s pass || Serviceability | NFR-043 pack replacement ≤ 15 min | Pass || DFM/DFA | ODM review; yield on 100 units ≥ 90 % first-pass at FCT | Pass | ### 3.4 Firmware scope at DVTFeature-complete job engine (all endpoints, resume, checksum, link policy, data caps, USB tethering (`ipheth`/NCM/RNDIS/MBIM) + hotspot metered-link handling), EC firmware v1 (incl. thermal safety state machine, Port B PD-present policy, Job Location GATT), Port C NWPC set-before-switch + consent flow behind the Pro feature flag, OTA, secure boot with production key ceremony rehearsal, factory test suite (Base; Pro tests flag-gated), iPhone app alpha for FR-060…064 and usability tests. ### 3.5 Exit criteriaAll P0 requirements verified at DVT stage on the Base population; environmental and battery reports in hand (drop on AZ91D shots); regulatory pre-compliance margins ≥ 3 dB; formal FCC/ISED/CE submissions made; **hard-tooling release (Mg die-cast tool, ODM-owned)**; final BOM and ODM quote; DVT→PVT ECO list < 10 items, none affecting tooling. Pro-track status reported but not gating. ### 3.6 Cost / time≈ **$345–500 k** (soft tooling ~$125 k incl. the **Mg thixomold / T0 soft tool ~$35 k (verify)**, PC and TPU soft tools, shutter and seal soft parts; PCB/assembly ~$80 k; environmental/regulatory pre-compliance/battery/salt-fog testing ~$95 k; antenna/LDS trials ~$25 k; packs ~$15 k; misc). Team adds: 1 test engineer (working with the ODM's fixture team), 1 compliance lead (contract), app developers (Phase 3). --- ## 4. PVT — Production Validation Test (months 12–15) ### 4.1 GoalsProve the *factory*: production tooling, line process, test coverage, yield, packaging, and final certifications; units are saleable if they pass. ### 4.2 Hardware built200–500 Base units on the production line at the ODM with hard tooling (**production AZ91D hot-chamber die-cast chassis with the production coating and masking**, PC+GF frame, TPU overmold, shutter stamping, seals), production packs with UN 38.3 certificate, LDS antennas (or flex if LDS trial failed), fused secure boot with production keys, laser-marked labels with FCC/ISED/CE IDs (grants from the DVT-1 campaign in hand; provisional marking plan only if a re-test is needed). Pro population runs as a line variant when the Pro track (Pro FCT fixture, Pro addendum) is ready — it does not hold the Base PVT. ### 4.3 What is validated | Area | Tests | Pass ||---|---|---|| Line | ICT/FCT/RF-calibration/final-audio-visual station cycle time ≤ 6 min/unit; first-pass yield ≥ 95 %; Cpk ≥ 1.33 on shutter force, IP leak test, RF TRP; Base fixture (Pro fixture separately on the Pro track) | Targets || Cosmetic | Colour/finish standards on coated castings (powder/e-coat, masked pads); drop-cosmetic acceptance | Pass || Regression — **mandatory on production castings (D4)** | 3 units repeat drop (26 drops); 5 units IP54; production AZ91D die-castings differ from the DVT soft-tool shots in porosity, ductility and coated parting lines, so this is a launch-gate re-test, not a spot check; 10 units 48 h burn-in per mode; NFR-021 spot check | Pass — Base launch gate || Regulatory | FCC/ISED/CE grants (tested on DVT-1 Base units, `11-certification.md` §11) confirmed against PVT units — no change affecting the radio host assessment; UKCA DoC; UL/IEC 62368-1 CB report; RoHS/REACH declarations incl. the Cr(VI)-free Mg coating | Grants issued, DoCs signed || Security | SAF-030 debug fusing verified on every unit; key ceremony executed; SAF-010…016 on production keys | Pass || Packaging | ISTA 3A drop/vibration on retail pack with device | Pass || Documentation | Service manual, factory test spec, golden units, ECO closure | Complete | ### 4.4 Exit criteriaYield and Cpk targets met; all certifications required for the launch region(s) granted for the Base population; PVT drop/IP re-test on production castings passed; ≤ 3 open non-blocking ECOs; MP purchase orders placed. Pro population released when its own line variant, fixture and regulatory addendum are complete (D7). ### 4.5 Cost / timeHard tooling ≈ **$195 k** (ADR §11; Mg die-cast tool ≈ +12 % vs the aluminum figure, verify; ODM-owned from DVT exit), PVT units ≈ $250–300 k at ~$600 each incl. line NRE, formal certifications ≈ $150–200 k (`11-certification.md`; the Pro addendum ~$8–15 k is inside that band). --- ## 5. MP — Mass Production (month 15+)Ramp to ~300 units/month at the ODM; monthly ORT (ongoing reliability test: 5 units, 1 week each, plus quarterly drop/IP on castings); ECO board; second-source qualification for the SoM (NFR-045) if a SoM was chosen at PoC exit; **Pro-SKU population change on line (ASM2464PD path + Port C PD sink + NVMe) when the Pro track is released**; post-launch: board-down RK3588 cost-down study if a SoM was chosen and run-rate exceeds 10 k/yr; PEO coating variant if a salt-fog/marine claim is wanted. --- ## 6. Tooling decision points and long-lead items | Item | Lead time | Decision gate | Notes ||---|---|---|---|| **Magnesium die-cast chassis tool (AZ91D, hot-chamber)** | ~14–16 weeks + 4 weeks T1 samples (verify with the ODM's caster) | Hard tool at DVT exit (month 12); ODM-owned | Machined AZ31B bridges EVT; **AZ31B conducts ~30 % better than AZ91D — correct EVT thermal data or use thixomolded units**; boss faces machined post-cast to 0.10 mm flatness || **Magnesium thixomold / T0 soft tool (AZ91D)** | 8–10 weeks (verify) | Release at EVT exit (month 7) | ~$35 k (verify); gives DVT drop/thermal units in production alloy || **Magnesium coating supplier qualification** (chromate-free conversion coat + powder/e-coat, masking; PEO alternate) | 8–12 weeks incl. coupon salt fog | Start at EVT kick-off via the ODM; qualified before DVT castings | Cr(VI)-free mandatory (RoHS); masking fixtures for bosses and gasket lands || PC+30 % GF front frame injection tool | 10–12 weeks | Soft tool at EVT exit; hard tool at DVT exit | RF windows and antenna LDS zones must be frozen before tool cut || TPU overmold tool | 8–10 weeks | DVT exit | Depends on frame tool || Shutter slats (stamped, hard-anodized 6061) + POM rails + detent hardware | 8 weeks | DVT exit | EVT uses machined equivalents; slats never touch the Mg chassis (POM tracks, silicone seals) || Silicone gaskets / RJ45 door / button | 6–8 weeks | DVT exit | || SoC carrier: Firefly Core-3588J **or** Forlinx FET3588-C **or** board-down RK3588J + LPDDR4x + PMIC (per PoC-exit decision) | SoM 8–12 weeks, industrial allocation; board-down: RK3588J allocation + DDR lead times 12–20 weeks | Volume PO at DVT exit | Lifecycle letter (NFR-045) requested from each candidate at PoC (bake-off C4) || 21700 cells with UN 38.3 + IEC 62133-2 reports | 8–12 weeks; pack vendor NRE 6 weeks | Pack vendor selected at EVT (via ODM) | Air-shipping uncertified packs is not allowed — plan ground freight for EVT/DVT || CFexpress B/A, SD UHS-II deep-insertion connectors | 6–10 weeks; some custom | Confirm at PoC | If a custom-depth CFe B connector is needed, add 12 weeks tooling || ASM2812 / ASM2464PD / ASM3142 / ASM1064 | Distributor stock; NDA + firmware tool access via the owner's ASMedia-access team (D12) | Engage at PoC start | Fallback: PEX8724 (switch) retained at EVT freeze; ASM2464PD RO configuration question answered at PoC (P14) || Port C PD parts (third TPS25750, TPS2121-class mux) — Pro only | Distributor stock | EVT (Pro track) | Verify mux rating at 20 V / 65 W || IP67 USB-C receptacles | 6–8 weeks | EVT | || LDS antenna development (Wi-Fi ×2, optional cost-down vs flex) | 10–14 weeks | Start at EVT with flex fallback | Wi-Fi only; drop if flex is cheaper at volume || MHF4 cable assemblies, custom lengths | 4–6 weeks | EVT | | --- ## 7. Team and vendor needs | Role / vendor | When | Notes ||---|---|---|| Lead systems/hardware architect | Throughout | Owns ADR || 2× EE (digital/high-speed; power/analog) | PoC → PVT | High-speed EE must have Gen4/USB4 layout experience; layout hands over to the ODM from EVT-B || 0.5× RF engineer (contract, part-time) + **antenna house** (Taoglas/Antenova/Ignion design services or a Shenzhen LDS house) | PoC (mock) → DVT | Wi-Fi/BLE only; also owns the Wi-Fi SAR pre-scan (unchanged in v0.3) || 1× ME + **industrial design studio** | PoC end → PVT | Shutter mechanism, seals and the magnesium coating/galvanic stack are the ME critical path || 2× firmware (Linux BSP; EC/Zephyr) | PoC → | Grows to 4 in Phase 2 || Test/manufacturing engineer | DVT → | Test specs and coverage; fixtures are built by the ODM || Compliance lead (contract) | DVT → | Drives the FCC/ISED/CE, battery and safety labs incl. the Pro addendum; see `11-certification.md` || **ODM / CM** with rugged/RF product experience (lined up, D12) | **Design review before EVT schematic (§2.0) → MP** | Owns layout/DFM from EVT-B, FCT/ICT fixtures, line NRE, hard tooling from DVT exit, Mg die-cast + coating and battery-pack supplier management; may supply the RK3588 board-down reference design; needs IP-test and RF-cal capability || **Accredited test lab** (radio + EMC + SAR + environmental), e.g., UL/Element/TÜV/Eurofins | EVT pre-scan → PVT | Book SAR and RED slots early || Battery pack vendor with UN 38.3/IEC 62133-2 experience | EVT (via ODM) | || PCB fab with Megtron 6/hybrid stackup capability | EVT | Two-spin budget; ODM's fab from DVT || Magnesium die-caster (hot-chamber AZ91D) + coating line | Coupons at EVT, soft tool at DVT, hard tool at PVT (via ODM) | Thixomold option for DVT | --- ## 8. Program cost estimate ### 8.1 Hardware program (excluding salaries and Phase 2/3 software) | Stage | v0.2 | **v0.3** | What moved ||---|---|---|---|| PoC | $20 k | **$20 k** | Extra SoC kits inside the rig budget || EVT | $110–150 k | **$120–160 k** | Machined-magnesium/SLA enclosures ~$35 k (was ~$25 k CNC aluminum), coupons || DVT (incl. soft tooling, environmental, battery certs) | $310–460 k | **$345–500 k** | Mg thixomold / T0 soft tool ~$35 k (verify), salt-fog testing || PVT units + line NRE | $250–300 k | **$250–300 k** | — || Hard tooling | ~$185 k | **~$195 k** | Mg die-cast tool ≈ +12 % vs aluminum (verify) || Formal certifications (FCC/ISED/CE incl. Wi-Fi SAR, UL, MIL/IP lab; Pro addendum inside the band) | $150–200 k | **$150–200 k** | — || **Total to MP** | ≈ $1.0–1.3 M | **≈ $1.1–1.4 M** | | ### 8.2 Full program cost view (ADR §11) — assumptions clearly labelled **Assumptions.** Fifteen months to MP; person-month (pm) rates are fully loaded (salary, benefits, overhead, tools). Two staffing scenarios: **US fully-loaded** at ~$18–22 k/pm with all engineering in-house; **ODM-supported / lower-cost** at ~$10–14 k/pm (lower-cost region and/or contract staff) *and* fewer person-months because the ODM does layout from EVT-B, DFM, fixtures and tooling management. The hardware program (§8.1) is the same in both scenarios (the ODM's NRE is already inside it). Phase 2/3 software is costed as effort bands, not as a plan. All figures are planning ranges, not quotes. **Phase 1 hardware staffing through MP (role × months):** | Role | US scenario — months | ODM-supported — months | Notes ||---|---|---|---|| Lead systems / hardware architect | 15 | 15 | Owns ADR in both || EE — digital / high-speed | 15 | 12 | ODM takes layout from EVT-B || EE — power / analog | 13 | 8 | ODM handles power-section DFM || Mechanical engineer | 14 | 10 | ODM manages Mg die-cast, coating, tooling || RF engineer (0.5 FTE × 12 months) | 6 | 4 | Contract in both || Firmware — Linux BSP + EC/Zephyr (2 FTE, bring-up / factory test / EC) | 28 | 28 | Same in both (Phase 2 job engine is separate below) || Test / manufacturing engineer | 9 | 3 | ODM builds fixtures || Compliance lead (0.5 FTE, DVT → MP) | 5 | 4 | Contract in both || Program manager (0.5 FTE) | 8 | 6 | || ID / CAD / documentation support | 7 | — | Absorbed by the ODM and ID studio || **Total person-months** | **≈ 120 pm** | **≈ 90 pm** | || **Cost at rate** | **≈ $2.2–2.6 M** (120 × $18–22 k) | **≈ $0.9–1.3 M** (90 × $10–14 k) | | **Program totals:** | Block | US fully-loaded | ODM-supported / lower-cost ||---|---|---|| Hardware program to MP (§8.1) | $1.1–1.4 M | $1.1–1.4 M || Phase 1 engineering staffing through MP (table above) | $2.2–2.6 M | $0.9–1.3 M || Phase 2 firmware (job engine, connectors, EC, OTA, security; ≈ 28–40 pm US / 25–32 pm low-cost) | $0.5–0.9 M | $0.25–0.45 M || Phase 3 apps (iPhone first, then desktop; ≈ 20–28 pm / 18–22 pm) | $0.4–0.6 M | $0.2–0.3 M || Subtotal | $4.2–5.5 M | $2.45–3.45 M || Contingency 20–25 % | $0.9–1.3 M | $0.5–0.8 M || **Total** | **≈ $5.5–6.5 M** | **≈ $3.2–3.9 M** | The quoted totals are the ADR §11 planning bands; the arithmetic extremes of the table (≈ $5.0–6.9 M and ≈ $2.9–4.3 M) include the unlikely all-low / all-high corners, which the bands trim. Ranges are deliberately wide at this stage. **Target retail price and total budget ceiling: not yet set by the owner** — gap analysis vs the BOM-implied MSRP band (`10-bom.md`) is deferred until they are provided. The levers, when that conversation happens, are volume (1 k vs 10 k pricing), SKU mix (Base vs Pro), ODM rates and scope (the two columns above), and deferring the Pro / Port C track. --- ## 9. Phase 2 hand-off — what firmware needs from hardware Delivered at EVT-B (draft) and DVT (final): 1. **Schematics and netlists** (PDF + source), with every strap/GPIO named per the pinmap; Base vs Pro population tables.2. **Pinmap and DT source**: complete device tree for the main board (PCIe bifurcation, all PCIe root ports, dwc3 role, GL9755/GL9750 quirks, RTL8126, MT7925, ASM3142 xHCI with the USB network-class drivers (`ipheth`, `cdc_ncm`, `rndis_host`, `cdc_mbim`, `qmi_wwan`), TPM SPI, OLED SPI on EC not SoC, I²C map for the three PD controllers, charger, VBUS priority mux status, eFuses, sensors).3. **EC ↔ SoC protocol specification**: UART framing, message set (power state, mode-switch request/ack, mux state, slot power, card-detect, gauge/charger telemetry, thermal requests, OLED content, LED patterns, BLE pairing events, RTC, location forward), timing guarantees for the mode-switch sequence (FR-043), watchdog contract.4. **Mode-switch sequence diagram** with exact GPIO/timing (PERST# ≥ 100 ms, power-off dwell 200 ms, mux settle, REFCLK switch, rescan trigger) — from `02-system-architecture.md`, validated at PoC P2.5. **NVMe Namespace Write Protection flow (D8):** Set Features 0x84 (state 1) issued by the SoC before the mux flip, NWPC capability check (Identify Controller byte 531), behaviour across the slot power cycle, and the per-card results table from P13 / the EVT card matrix.6. **Port C consent UX (D8):** the decision tree (NWPC → bridge WP → consent), OLED/app prompt wording ("Mac wants write access to CFe B — allow?"), button-hold / app-toggle semantics, session logging, and the on-return re-verification report (identity + directory/mtime scan, changed/added files).7. **Job Location GATT characteristic (D13):** vendor UUID, payload (lat, lon, alt, horizontal accuracy, timestamp, source), write-with-response, bonded/encrypted link requirement, the equivalent NCM management-API endpoint, and the job-metadata / manifest / sidecar fields it populates.8. **Port B PD-present policy (D13):** the EC rule (1.5 A on battery, 3 A only with a PD source present on Port A — or Port C on Pro — 0.5 A selectable), the signals it is derived from, and how the SoC/app reads and requests the setting.9. **Thermal-safety state machine (D2):** sensor IDs and thresholds (52 °C skin / 60 °C air / 55 °C battery / component limits → checkpoint → slots and radios off → standby; resume at ≤ 42 / 45 °C with link and cards present), the job-engine checkpoint contract, OLED text, BLE notification, and the relationship to the throttle ladder (item 11) and the 48 °C mechanical switch.10. **Power-state table**: rails per mode, which devices are power-gated in standby, wake sources, gauge thresholds (5 % / 3 %) and the EC's hard-off contract; Port C sink / Port A priority behaviour on Pro.11. **Thermal sensor map and throttle table** (NFR-032) with sensor IDs and hysteresis, shutter open/closed variants.12. **Secure-boot key hierarchy** and OTP layout; TPM PCR usage; RAUC slot layout on eMMC; LUKS2 partition plan; EC MCUboot key plan.13. **Factory test interface**: test-mode entry, per-interface loopback/BER tests, RF calibration hooks, fusing procedure; Base vs Pro (feature-flagged) test sets.14. **Card and host compatibility matrix** results (IF-001…006, FR-046) with observed quirks (e.g., cards that need longer PERST#, hosts that need BOT instead of UAS, NWPC support per card).15. **Measured power table** (ADR §6.1 re-issued) so the runtime estimator (FR-073) can be seeded before field data exists.16. **Tethering integration notes**: supported phones/adapters (tested matrix from PoC P7), drivers, iOS trust-prompt flow, Port B current-limit policy (item 8), metered-link defaults, data counters (FR-025).17. **Regulatory constraints for software**: power-table limits per band/region, 6 GHz AFC/LPI rules, SAR duty-cycle limits if any, "airplane mode" behaviour.