docs/09-pcb-architecture.md
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PoppyUp — PCB Architecture
Document: 09 of 13 — Phase 1 Hardware Design
Revision: v0.3 — aligned to ADR Baseline v0.3 (owner decisions D1–D13, ADR §15). v0.3 changes here: Port C PD sink + VBUS priority mux (Pro population), magnesium chassis interfaces, board-down RK3588J option noted, Base/Pro FCT split, 5GbE only.
Source of truth: 00-architecture-decisions.md (ADR §3, §6, §7, §8, §9).
Related: 02-system-architecture.md (topology and mode-switch signals), 05-power-budget.md (rails), 06-thermal.md (heat paths), 07-rf-antenna.md (keep-outs), 08-mechanical.md (envelope, connector positions), 10-bom.md.
1. Board set and partitioning
| Board | Layers | Approx. size | Contents | Why a separate board |
|---|---|---|---|---|
| Main board (MB) | 10, hybrid laminate | 165 × 80 mm, 1.6 mm | SoM connectors, ASM2812 switch, PI3DBS16412 + clock mux, ASM2464PD, ASM3142, RTL8126 + magnetics, M.2 Key-E (Wi-Fi), M.2 M-key (NVMe), PD controllers ×3 (TPS25750: Port A sink/source, Port B source, Port C sink) + TPS2121-class VBUS priority mux — the Port C controller and mux are Pro population only (D7), BQ25792 charger, dedicated 5.0 V/3 A Port B buck (TPS62933 class) with EC-programmable current limit, all bucks/LDOs, TPM SLB9672, nRF5340 EC, USB-C ×3, RJ45, mezzanine (male), OLED/LED/button/Hall/antenna connectors. v0.1's M.2 Key-B modem slot and SIM tray are removed (ADR §14). | Everything with a high-speed path to the SoC and everything that dissipates heat lives on the one board pressed against the magnesium rear skin (AZ91D die-cast at production, machined AZ31B / thixomolded AZ91D at EVT/DVT, D4). |
| Reader daughterboard (RB) | 8, FR-4 Tg170 | 180 × 38 mm, 1.6 mm | 5 card connectors, GL9755, GL9750, ASM1064, 5× eFuse, card-detect, Hall sensor, LED bar, mezzanine (female) | The slot row must sit exactly at the top edge under the shutter with tight mechanical tolerances; a separate board lets the slot line-up be a mechanical part. It also makes the no-CFast (150 mm) and dual-CFe-B variants a board swap, not a main-board re-spin. Card connectors are the highest-wear items; a daughterboard is field-replaceable at service depots. |
| Battery pack PCB (PB) | 2, FR-4 | 60 × 25 mm | BQ40Z50-R2 gauge/protector, BQ294xx secondary protector, fuse, 2× NTC, pack connector, cell tabs | Part of the UN 38.3 / IEC 62133-2 certified pack assembly; must be certifiable independently of the rest of the product. |
| Flexes | 1–2 | — | OLED FPC (module-supplied), button/Hall flex, 2× MHF4 antenna cables (Wi-Fi; not flex PCBs), optional LED-bar flex if the bar is not on RB | Mechanical routing only. |
The SoM itself is a fourth PCB we buy, not design. The RK3588 BGA, LPDDR4x and PMIC are thereby off our critical path; the main board is a carrier. Board-down option (D12): the SoM is undecided — a PoC bake-off of Firefly Core-3588J, Forlinx FET3588-C and a board-down RK3588J on the ODM's reference design. If PoC exit selects board-down, the SoM connector footprint area in §1.1 becomes the RK3588J + LPDDR4x + RK806 PMIC region on a likely 12-layer main board — a major EVT layout delta (DDR routing, power sequencing, boot media) that this document notes but does not redesign for; the rest of the architecture (switch, mux, ports, power) is unchanged.
1.1 Placement sketch — main board (component side toward the rear magnesium skin)
<-------------------------------- 165 mm -------------------------------->
+-------------------------------------------------------------------------+
| MEZZ (to RB) ASM1064/GL975x are on RB PI3DBS16412 ASM2464PD | top edge
| 80-pin ADM6 ------------------------ clk mux + SPI flash | (toward slots)
| |
| +-----------------------------+ ASM2812 RTL8126 M.2 Key-E |
| | RK3588 SoM (Core-3588J) | switch + xfmr 2230 Wi-Fi | 80 mm
| | 70 x 55 mm, 2x B2B conn | (heatpad) (shield) (keep-out) |
| +-----------------------------+ |
| bulk caps / power spread (ex-modem) |
| TPM nRF5340 EC ASM3142 +---------------------------------+ |
| + chip ant | M.2 M-key 2280 NVMe (Pro SKU) | |
| BQ25792 bucks bucks bucks +---------------------------------+ |
| PD-A PD-B PD-C + VBUS mux (Pro) PortB-BUCK spare PCIe hdr |
| [USB-C A][USB-C B][USB-C C] [RJ45 + door] | bottom edge
+-------------------------------------------------------------------------+ (ports)
Rules encoded in this sketch:
- The ASM2464PD, PI3DBS16412 and the mezzanine cluster at the top edge, nearest the CFe B connector on the RB, to keep the Gen4 mux path short (§4.2).
- The ASM2464PD → Port C run is the longest USB4 trace and is the one exception: Port C is at the bottom edge. Mitigation: Port C is placed at the right end of the port row and the ASM2464PD at the right end of the top edge, giving a straight ≤ 60 mm run down the right margin on low-loss laminate (§4.1). If EVT S-parameter measurements show margin problems, the fallback is to move Port C to the right long side near the top (mechanical change only).
- M.2 slots are on the rear-facing side so their thermal pads press against the magnesium skin.
- PD-C + VBUS mux sit between the Port C receptacle and the charger so the Port C VBUS → TPS2121 → BQ25792 input run is short and its inductance low (break-before-make transient, §12 item 10). Both parts are Pro-only population; on Base the footprints are empty and a 0 Ω jumper (or the mux's Port A path shorted) feeds the charger from Port A alone.
- The ~30 × 52 mm area freed by the v0.1 M.2 Key-B modem slot (X 104–134 in the enclosure frame, right of the SoM and above the NVMe slot) is used to spread the power section and add bulk capacitance (5.0 V and VSYS), and to house the spare PCIe Gen2 test header. The 165 × 80 mm outline is unchanged in v0.2; shrinking the board is an EVT option (ADR §9).
- The SoM is centred; its two board-to-board connectors put the ×4 and ×2 Gen3 lanes on the side facing the switch and mux.
- Switchers cluster bottom-left, away from the Wi-Fi module and antenna cable exit points (right and top).
- The EC and its BLE chip antenna sit at the bottom-left corner behind a PC window (see
07-rf-antenna.md).
1.2 Placement sketch — reader daughterboard (slot side up)
<---------------------------------- 180 mm ---------------------------------->
+------------------------------------------------------------------------------+
| [ CFast 2.0 ] [ CFexpress B ] [ CFe A ] [ SD UHS-II ] [ uSD ] LED bar | top = card entry
| 45 mm 40 mm 22 mm 27 mm 13 mm x5 |
| ASM1064 eFuse eFuse Hall eFuse GL9755 eFuse GL9750 eFuse | 38 mm
| [========= 80-pin ADM6 mezzanine to MB =========] card-detect |
+------------------------------------------------------------------------------+
Gaps between slot housings are 4 mm (ADR §7); the row is ≈ 163 mm; board is 172 mm to give clearance to the enclosure ribs and the 10 mm end-cap zones (shutter rail grooves and drains; no longer RF windows) at each end.
2. Stackups
2.1 Main board — 10 layers, hybrid
| Layer | Purpose | Material below | Notes |
|---|---|---|---|
| L1 | Component side (rear-facing): SoM connectors, M.2 slots, switch, ASM2464PD, USB4/Gen4 escape | Megtron 6 prepreg | Only short escapes here; thermal pads |
| L2 | GND | Megtron 6 core | Reference for L1 and L3 |
| L3 | High-speed signal 1: USB4 (ASM2464PD → Port C), Gen4 mux path | Megtron 6 prepreg | 85 Ω diff, stripline, ≤ 4 pairs in flight |
| L4 | GND | FR-4 Tg170 core | Reference for L3 and L5 |
| L5 | High-speed signal 2: PCIe Gen3 from SoM to switch and mux, Gen3 to M.2 slots | FR-4 Tg170 prepreg | 85 Ω diff stripline |
| L6 | Power planes: 5.0 V, 3.3 V logic, 3.3 V slots (split with wide moats, no HS crossing) | FR-4 Tg170 core | |
| L7 | Power planes: VSYS, 1.8 V; local 1.05/1.2 V islands (the v0.1 3.3 V modem-rail region becomes additional VSYS/5.0 V plane area) | FR-4 Tg170 prepreg | |
| L8 | GND | FR-4 Tg170 core | Reference for L7 and L9 |
| L9 | High-speed signal 3: USB 3.2 Gen1 (OTG1 → Port A), USB 3.2 Gen2 (ASM3142 → Port B), Ethernet MDI, Gen2 lane to Key-E (and the spare pcie2x1l0/pcie2x1l2 lanes to the test header) |
FR-4 Tg170 prepreg | 90 Ω USB, 100 Ω MDI, 85 Ω PCIe |
| L10 | Component side (front-facing): passives, EC, PD controllers, USB-C/RJ45 receptacles, connectors to OLED/LED/button | — | Low-profile parts only under the battery volume |
Copper: 1 oz outer, 0.5 oz inner signal, 1 oz inner power. Overall 1.60 mm ± 10 %. The hybrid is Megtron 6 (or Isola I-Speed) for L1–L4 only, which keeps laminate cost to roughly +25 % over full FR-4 rather than +80 % for an all-Megtron board. Alternative if the fab objects to hybrid bonding: full Isola I-Speed (Df ≈ 0.006) at a modest premium; it meets the USB4 budget with less margin.
Target impedances (differential, ± 10 %):
| Net class | Zdiff | Zsingle | Layer |
|---|---|---|---|
| PCIe Gen3/Gen4 lanes, USB4 lanes | 85 Ω | 42.5 Ω | L3, L5 |
| USB 3.2 Gen1/Gen2 SuperSpeed | 90 Ω | 45 Ω | L9 |
| USB 2.0 D+/D− | 90 Ω | — | L9 |
| Ethernet MDI (4 pairs) | 100 Ω | — | L9 |
| PCIe REFCLK 100 MHz HCSL | 100 Ω | — | L5 (SoC side), L3 (bridge side) |
| SDIO/SPI/UART/I²C | — | 50 Ω | any |
2.2 Reader daughterboard — 8 layers, FR-4 Tg170
| Layer | Purpose |
|---|---|
| L1 | Card connectors, eFuses, controllers |
| L2 | GND |
| L3 | High-speed: CFe B Gen3 ×2 (mux side is Gen4-capable: keep ≤ 40 mm), CFe A Gen3 ×1, SATA to CFast, UHS-II pairs |
| L4 | Power: 3.3 V slots (per-slot islands after eFuses), 1.8 V UHS-II |
| L5 | Power: 3.3 V logic, 1.2 V ASM1064 core |
| L6 | GND |
| L7 | High-speed: Gen3 ×1 lanes to GL9755, GL9750, ASM1064; REFCLKs |
| L8 | Mezzanine connector, card-detect, LED bar, Hall |
The CFe B pairs run from the connector straight to the mezzanine on L3 with one reference plane each side, no layer change other than the connector escape. The daughterboard's contribution to the Gen4 mux path budget is capped at 40 mm of trace (§4.2).
2.3 Battery pack PCB — 2 layers, 2 oz copper, 1.0 mm
Nothing high speed. Layout priority is the current path (10 A continuous, 20 A fuse) and creepage per IEC 62133-2.
3. Material and loss budgets
3.1 USB4 Gen3 path: ASM2464PD → Port C
- Symbol rate 20 GBd per lane (NRZ), two lanes each direction. Assess at 10 GHz Nyquist.
- Channel budget from the USB4 spec for the device side board (receptacle to chip) is tight; we allocate ≤ 4 dB at 10 GHz including the receptacle.
- Megtron 6 stripline at 10 GHz: ≈ 0.55 dB/inch (0.022 dB/mm) at 4-mil trace width with smooth copper. 60 mm → 1.3 dB. Receptacle (IP67 mid-mount USB-C, USB4-rated) ≈ 0.8–1.2 dB. Two layer-transition vias, back-drilled, ≈ 0.3 dB. AC-coupling capacitor footprints ≈ 0.2 dB. Total ≈ 2.6–3.0 dB, leaving 1 dB margin for etch variation. Maximum route length is therefore fixed at 60 mm; the placement in §1.1 delivers ≈ 55 mm.
- Reverse-treated (VLP) copper foil is mandatory on L1–L4; standard copper roughness costs another 0.15 dB/inch at 10 GHz and eats the margin.
3.2 PCIe Gen4 mux path: CFe B connector ↔ PI3DBS16412 ↔ ASM2464PD
- 16 GT/s, assess at 8 GHz. PCIe Gen4 end-to-end budget is 28 dB, but the card consumes the add-in-card allocation (≈ 8 dB), and the ASM2464PD RX has a fixed CTLE/DFE capability; we allocate ≤ 8 dB at 8 GHz for our portion.
- Segments: RB connector → RB trace (≤ 40 mm FR-4 Tg170, ≈ 0.75 dB/inch at 8 GHz → 1.2 dB) → mezzanine (ADM6/ADF6, ≈ 0.5 dB) → MB L3 trace to mux (≤ 30 mm Megtron 6 → 0.5 dB) → PI3DBS16412 (≈ 1.5 dB insertion loss at 8 GHz, per family datasheet class) → MB L3 trace to ASM2464PD (≤ 50 mm → 0.9 dB) → vias/AC caps (0.5 dB). Total ≈ 5.1 dB, comfortably inside 8 dB. Total trace length ≤ 120 mm is the layout constraint.
- The SoC side of the same mux only trains at Gen3 (8 GT/s, assess at 4 GHz), where the budget is generous; SoM → mux may be up to 100 mm on L5 FR-4 without concern.
3.3 PCIe Gen3 paths on FR-4
- 8 GT/s, assess at 4 GHz. FR-4 Tg170 (Df ≈ 0.014) stripline ≈ 0.45 dB/inch at 4 GHz.
- Budget per path (root to endpoint, our board portion) 8 dB. 250 mm of trace = 4.4 dB, plus connectors and vias ≈ 1.5 dB → 6 dB. The longest Gen3 route is SoM → switch → M.2 M-key: ≈ 180 mm total; SoM → switch → mezzanine → GL9755 ≈ 220 mm. Both pass. No retimers or redrivers anywhere in the design.
3.4 USB 3.2 Gen2 (ASM3142 → Port B) and Gen1 (SoM → Port A)
- Gen2: 10 Gb/s, 5 GHz. Budget 6 dB board-side. 90 mm on L9 FR-4 → 2.2 dB + receptacle 1 dB + vias 0.5 dB → 3.7 dB. Pass.
- Gen1: 5 Gb/s, trivially fine at any length on this board.
3.5 Ethernet MDI
- RTL8126 to magnetics ≤ 25 mm, magnetics to RJ45 ≤ 15 mm, 100 Ω. Discrete magnetics (not an integrated MagJack) because the RJ45 needs a chassis-anchored shroud and gasket, and because 5GBASE-T magnetics are specified separately from the jack. 5GBASE-T MDI is 200 MHz-class signalling; FR-4 is fine, but inter-pair skew and common-mode chokes matter (§6).
4. High-speed layout rules
| Rule | Gen4 / USB4 class | Gen3 / USB 3.2 class |
|---|---|---|
| Intra-pair length match | ≤ 5 mil (0.13 mm) | ≤ 10 mil (0.25 mm) |
| Inter-pair skew (within a link) | not required by PCIe/USB4 (lane de-skew); keep ≤ 5 mm for layout hygiene | same |
| Trace geometry | 4/6/4 mil stripline, Megtron 6 | 4.5/7/4.5 mil stripline, FR-4 |
| Layer changes per pair | ≤ 2, back-drilled | ≤ 3 |
| Return-path via | 1 GND via within 0.5 mm of every signal via, both pairs | same |
| Reference plane | unbroken GND both sides; never route over a power split | same |
| AC-coupling | 220 nF 0201 on every TX pair at the transmitter end (PCIe rule: AC caps belong to the TX side; for the CFe B slot the card carries its TX caps and we place caps on our TX toward the card, i.e. on the mux-input side from both SoC and ASM2464PD) | same; USB 3.2 has caps on TX per spec |
| Stub length | back-drill all through-vias on L3 nets; stub ≤ 0.2 mm | ≤ 0.5 mm, back-drill optional |
| Bend radius | 45° or arc, ≥ 3× trace width | same |
| Fibre-weave mitigation | 10° route angle or zig-zag on straight runs > 25 mm (Megtron 6 spread glass 1078 preferred) | not required |
| Coupling to other nets | ≥ 3× dielectric height to any other trace; ≥ 5× to switchers' nets | same |
| Test points | none on Gen4/USB4 nets (use connector probing) | none |
4.1 REFCLK distribution and the clock mux
- The RK3588 supplies one 100 MHz HCSL REFCLK per root port. The
pcie3x4REFCLK goes to input A of a 2:1 HCSL clock mux (Diodes PI6C59S6005 class or equivalent low-jitter 2:1 buffer/mux); the ASM2464PD's downstream REFCLK output goes to input B. The mux output drives the CFe B slot's REFCLK pins via the mezzanine. - The
pcie3x2REFCLK is fanned out to the ASM2812, which regenerates a REFCLK per downstream port (common-clock architecture). No SRIS/SRNS anywhere. - HCSL pairs are 100 Ω differential, series 33 Ω + 49.9 Ω shunt termination at the source per HCSL, length-matched ≤ 10 mil, routed on the same layer as the associated data lanes and kept ≥ 5× spacing from them.
- Additive jitter budget for the clock mux: ≤ 0.5 ps RMS (PCIe Gen4 refclk budget is 0.5 ps RMS after filtering; a buffer/mux with 0.1–0.2 ps additive is required). This is a selection criterion — verify against the chosen part's datasheet.
4.2 Antenna and RF keep-outs
- No traces or copper within 3 mm of MHF4 receptacle footprints on the M.2 cards' side; antenna cables exit the board edge through notches.
- The nRF5340 chip antenna has a 6 × 12 mm copper-free zone extending to the board edge, per the antenna vendor's reference; the PC window in the enclosure is aligned to it (
07-rf-antenna.md). - The M.2 Key-E module's own antenna connectors face the board edge nearest the Wi-Fi flex antennas in the front PC frame's upper band (ADR §8) to minimise cable length (≤ 120 mm).
5. Power integrity
5.1 Rail summary on the main board
| Rail | Source | Current | Consumers | Decoupling strategy |
|---|---|---|---|---|
| Charger input VBUS_IN 5–20 V | Pro: TPS2121-class priority power mux ORing Port A VBUS (priority) and Port C VBUS, break-before-make; Base: Port A VBUS through a 0 Ω bypass (mux and Port C PD controller depopulated, D7) | ≤ 3.25 A (65 W at 20 V; verify mux rating; 100 W tolerated on Port A only) | BQ25792 VBUS input | 2× 22 µF + TVS at the mux output; the mux's break-before-make gap is ridden by the charger input capacitance (no glitch into the NVDC path, §12 item 10) |
| VSYS 6–8.4 V | BQ25792 NVDC output | ≤ 8 A | all bucks, EC LDO | 2× 220 µF polymer + 10× 10 µF near charger; bulk supports PD-unplug transient |
| 5.0 V SYS | buck 6 A | ≤ 3.1 A (SoM 8 W + Port A 1.5 A source + OLED) | SoM input, Port A source (1.5 A), OLED | 4× 47 µF + 0.1 µF per load |
| 5.0 V PORT B | buck 3 A (TPS62933 class), in the freed ex-modem area | ≤ 3 A | Port B VBUS through the Port B eFuse; EC sets the 0.5 / 1.5 / 3 A limit (Rp + eFuse ILIM) and can cut it for the low-battery/thermal ladders (ADR §4.3, §6; 05-power-budget.md §3.3) |
2× 47 µF polymer + 4× 10 µF at the buck output to ride a 3 A attach step; kept off the SoM rail so phone charge-current steps do not couple into it |
| 3.3 V slots | buck 4 A | 4 A | eFuses → 5 slots (via mezzanine, 8 pins) | 22 µF at each eFuse input, 47 µF at each CFe slot output |
| 3.3 V logic | buck 4 A | ≤ 3.1 A (Pro peak) | ASM2812 I/O, RTL8126, M.2 Key-E, ASM3142, GL975x (via RB), PD controllers | distributed 10 µF + 0.1 µF |
| 1.8 V | buck 1 A | 0.6 A | UHS-II, TPM, misc I/O | local |
| 1.05 V, 1.2 V | local bucks (one per chip) | ≤ 1.5 A each | ASM2812 core, RTL8126 core, ASM2464PD core, ASM3142 core | each chip gets its own point-of-load buck ≤ 15 mm away; cores are noise-sensitive |
| 3.3 V AON | LDO from VSYS | 100 mA | nRF5340, Hall, RTC | 10 µF |
5.2 Card-slot power
- Each slot has an eFuse (TI TPS2596 class: adjustable current limit, soft-start, fault flag, reverse-current blocking). Limits: CFe B 2.5 A, CFe A 1.5 A, CFast 1.0 A, SD 0.8 A, microSD 0.5 A.
- Inrush. A CFe B card presents up to ~100 µF plus a controller that draws a 2–3 A wake-up spike. The eFuse soft-start ramps 3.3 V over 1–2 ms, capping inrush at the programmed limit and preventing the 3.3 V slot rail from dipping and glitching neighbouring slots. Hot insert therefore never disturbs another card mid-transfer.
- Card-detect pins go to the EC (interrupt) and the eFuse enable logic so that a slot is powered only with a card present. This also guarantees the "card removed while in host mode" case (
02-system-architecture.md§6.7) cuts power within microseconds. - The CFe B slot's 3.3 V is the one that must survive the mode-switch power-cycle sequence: the eFuse output has an active discharge (built into TPS2596 class) so a 200 ms off-dwell fully discharges the card.
5.3 ESD/TVS
| Location | Protection | Class |
|---|---|---|
| USB-C A/B/C SuperSpeed pairs | ultra-low-capacitance 4-ch TVS, ≤ 0.3 pF | TI TPD4E05U06 or Semtech RClamp0524P class; USB4 port uses a ≤ 0.2 pF part (TPD4E02B04-class) |
| USB-C CC1/CC2, SBU | TPD1E10B06 class per line | 22 V-tolerant on CC |
| USB-C VBUS | TVS 24 V standoff + load switch OVP; Port C VBUS (Pro): TVS at the receptacle ahead of the TPS2121 mux input, mux OVP/reverse-current blocking toward the released port; on Base the receptacle-side TVS stays populated with the mux absent | |
| USB 2.0 D+/D− | TPD2E001 class | |
| RJ45 MDI | 100 Ω pairs through magnetics; Bob Smith termination 75 Ω + 1 nF/2 kV on unused/centre taps; TVS on the chip side of the magnetics (TPD4E1B06 class) | |
| Card slots (all pins to card) | CFe B/A: 4-ch ≤ 0.3 pF TVS on each lane pair, plus CLKREQ/PERST; SD/microSD: 8-ch TVS array (TPD8E003 class) on data/CMD/CLK; CFast: 4-ch on SATA pairs | Card slots are user-touched with every insertion; treat as external |
| Button, Hall | series 1 kΩ + TVS |
5.4 Interlock hardware
The mode-switch interlock from 02-system-architecture.md §8 is a single 74LVC1G373 (transparent latch): D = EC MUX_SEL, LE = NOT CFEB_PWR_EN_SENSE (sense pin from the eFuse's power-good), Q → PI3DBS16412 SEL and clock-mux SEL. Place it adjacent to the mux; it is the only piece of "logic" on the board and it is deliberately not programmable.
6. EMI / EMC
- Shield cans over the RTL8126 + its magnetics side, over the ASM2812, and over the ASM2464PD. Cans are soldered fences with removable lids (rework at EVT) and are grounded to L2 with vias every 3 mm.
- Chassis grounding. The main board is screwed to the magnesium chassis at 8 points; each screw boss lands on an exposed L1 GND ring with 6 vias. The boss faces and EMI-gasket lands are masked, bare conversion-coated magnesium (no powder coat) so the bond is conductive; screws are zinc-nickel-plated steel or aluminum into aluminum / Zn-Ni inserts, never stainless into Mg (D4; verify contact resistance after 500 h salt fog at EVT). USB-C and RJ45 shells bond to the chassis through their brackets (§8) and to board GND at the connector. This single-point-per-connector chassis bond keeps ESD current on the chassis, not through the board. The battery negative is bonded to board GND at one point near the charger.
- RJ45 magnetics are placed within 15 mm of the jack, chassis-side (L1), with the isolation moat (2 mm) in all layers between the line side and logic side; Bob Smith terminations return to chassis ground, not logic ground.
- Switching regulators are grouped bottom-left with input loops minimised; the 6 A 5 V buck and the two 4 A 3.3 V bucks use shielded inductors. Switch nodes are on L10 with a solid L8 GND beneath; no high-speed traces on L9 pass under a switch-node area.
- Antenna cable routing. Both MHF4 (Wi-Fi) cables leave the board at the top and right edges and route in dedicated channels moulded into the chassis, never across the power section.
- Clock spreading. RK3588 SSC on PCIe REFCLK is enabled (common-clock architecture permits it, and the ASM2812 forwards it); the ASM2464PD path uses its own SSC. This buys ~5–8 dB on the 100 MHz harmonics that fall in the Wi-Fi 2.4/5 GHz bands and at the BLE radio (2.4 GHz).
- Card slots as apertures. The metal shutter and the connector cages are grounded to the RB GND, which is bonded to the chassis via the RB's mounting rail. This matters for radiated emissions with the shutter open.
7. Thermal design at PCB level
Heat sources and their conduction paths (numbers from ADR §6.1):
| Source | Typical W | Path to chassis |
|---|---|---|
| RK3588 SoM | 5.5–8 | SoM carries its own heat spreader; gap-pad from spreader to a masked, bare conversion-coated magnesium boss on the chassis rear skin. The ~2 mm rear-face slack (D3) goes into this interface: the SoM boss is raised ~2 mm and the pad is specified thicker and more compliant (2.0 → ~3.0 mm nominal at 30–50 % compression, verify at EVT), so the tolerance stack is absorbed in pad, not air. The SoM is the hottest sustained source (the v0.1 modem, 4.5–6 W, is gone). Board-down RK3588J (if chosen at PoC exit) pads the SoC lid directly to the boss |
| ASM2812 | 1.8 | Thermal vias (≥ 36, 0.3 mm) under the die pad into L2/L4 copper; 1.0 → ~1.5 mm gap-pad (verify) from can lid to a masked bare-conversion boss |
| RTL8126 + magnetics | 1.9 | Same via pattern; ~1.5 mm gap-pad on can lid to a masked bare-conversion boss |
| ASM2464PD (host mode only) | 2.0 | Via pattern; can-lid pad |
| CFe B card | 3–5 | On the RB: the connector cage is a metal frame; a copper pour under the slot with 40 thermal vias to L2, and a gap-pad from the RB back side to a chassis rib that runs under the slot row |
| Bucks | ~1.5 total | Ground pours + vias |
- Boss finish. Every gap-pad boss face is machined after casting to 0.10 mm flatness and masked during powder/e-coating so the pad sits on bare conversion-coated magnesium — a 40–60 µm organic coat under the 8 W SoM boss would add ~5 K (verify). AZ91D (k ≈ 72 W/m·K) spreads ~30 % less well than the machined AZ31B EVT chassis; EVT thermal data is corrected before the fan gate (D4, D5).
- Copper coins are not used in v0.3 (cost, fab risk). If DVT thermal shows the switch or PHY exceeding junction limits, embedded coins under the ASM2812 and RTL8126 are the upgrade; the footprints leave room.
- Thermistors (to the EC, NTC 10 k): SoM edge, at the ASM2812 can, at the RTL8126 can, at the CFe B cage on the RB, and on the pack PCB; one spare NTC channel is kept on the EC (the v0.1 modem thermistor). A separate 48 °C mechanical thermal switch on the chassis inner wall provides THERM_ALERT independent of firmware.
8. Mezzanine connector: Samtec ADM6/ADF6, 0.635 mm, 80 pins
Chosen because it is rated for PCIe Gen4 / 16 GT/s (with published S-parameters), has a stack-height range that lets the RB sit 5–8 mm above the MB, comes with guide posts and a positive-latch option, and is a mainstream part with multiple stack heights on the same footprint. Alternative: Hirose FX23 (Gen3 rated, cheaper) if the Gen4 path is de-scoped.
8.1 Pin allocation (80 pins: 2 rows × 40)
| Pins | Signal group | Count | Notes |
|---|---|---|---|
| 1–8 | CFe B PCIe lane 0/1 TX/RX (4 pairs) | 8 | Gen4-capable; ground pins interleaved per Samtec ground pattern (counted in GND) |
| 9–10 | CFe B REFCLK+/− | 2 | HCSL, from clock mux |
| 11–13 | CFe B PERST#, CLKREQ#, WAKE# | 3 | To/from EC |
| 14–17 | CFe A PCIe lane 0 TX/RX (2 pairs) | 4 | Gen3 |
| 18–19 | CFe A REFCLK | 2 | From ASM2812 downstream |
| 20–22 | CFe A PERST#, CLKREQ#, WAKE# | 3 | |
| 23–26 | GL9755 lane (2 pairs) | 4 | Gen3 |
| 27–28 | GL9755 REFCLK | 2 | |
| 29 | GL9755 PERST# | 1 | |
| 30–33 | GL9750 lane (2 pairs) | 4 | |
| 34–35 | GL9750 REFCLK | 2 | |
| 36 | GL9750 PERST# | 1 | |
| 37–40 | ASM1064 lane (2 pairs) | 4 | |
| 41–42 | ASM1064 REFCLK | 2 | |
| 43 | ASM1064 PERST# | 1 | |
| 44–51 | 3.3 V slots | 8 | ≥ 6 A total (0.75 A/pin rating on 0.635 mm; derated) |
| 52–53 | 3.3 V logic | 2 | for GL975x/ASM1064 |
| 54 | 1.8 V | 1 | UHS-II I/O |
| 55–59 | CFEB/CFEA/SD/USD/CFAST_PWR_EN | 5 | From EC |
| 60 | SLOT_FAULT# | 1 | Wired-OR |
| 61–65 | SLOT_DET[4:0] | 5 | To EC |
| 66 | HALL | 1 | |
| 67 | LED_DATA | 1 | |
| 68–69 | I²C (SDA/SCL) | 2 | EC bus for RB EEPROM (board ID/variant) and eFuse telemetry |
| 70 | NTC_CFEB | 1 | Analog |
| 71 | RB_PRESENT# | 1 | Tied to GND on RB |
| 72–80 | GND | 9 | Plus the ground pins of the connector's ground pattern; Samtec ADM6/ADF6 provides additional ground contacts in the shield/rows depending on variant — confirm exact pin numbering against the chosen variant's drawing at schematic capture |
The signal-to-ground ratio on the high-speed pairs must follow Samtec's recommended pattern (one GND between adjacent pairs); the table above lists logical allocation, and the physical assignment is finalised from the connector's S-parameter model during layout.
9. Connector tables
9.1 Main board
| Ref | Function | Part class | Notes |
|---|---|---|---|
| J1, J2 | SoM board-to-board | Per the SoM chosen at PoC exit (D12); v0.2 default Firefly Core-3588J (100-pin 0.5 mm B2B set — confirm count against the module drawing); Forlinx FET3588-C uses 4× 80-pin; board-down RK3588J has no J1/J2 | Mating height per SoM |
| J3 | Mezzanine to RB | Samtec ADM6-40-01.5-x-x-2 (male, 80 pos.) | Stack height chosen at layout |
| J4 | Port A USB-C | IP67 sealed mid-mount receptacle, USB 3.2 Gen1/PD, e.g. Amphenol 12401610E4#2A-class or GCT USB4165-class | PD sink up to 100 W |
| J5 | Port B USB-C | IP67 sealed mid-mount, USB 3.2 Gen2 | 5 V/3 A source |
| J6 | Port C USB-C | IP67 sealed mid-mount, USB4 40 Gb/s rated (same receptacle part as J4/J5, fitted on both SKUs) | Data role Pro SKU only; on Pro the receptacle also carries the PD sink (third TPS25750 + TPS2121-class mux into the charger input, D7) — no receptacle change. Verify a sealed USB4-rated receptacle is sourceable; fallback is a standard USB4 receptacle plus a gasket boot |
| J7 | RJ45 | Shielded, tab-down, through-hole, no magnetics, e.g. Amphenol RJHSE-5380-class | Discrete 5GBASE-T magnetics (Pulse H5007NL-class) |
| J8 | M.2 Key-E 2230 | 75-pos M.2 socket, 4.2 mm | |
| J9 | M.2 M-key 2280 | 75-pos M.2 socket, 4.2 mm | Empty on base SKU |
| J10 | OLED FPC | 30-pin 0.5 mm FPC (per SSD1309 module) | |
| J11 | Button/Hall flex | 6-pin 0.5 mm FPC | Front frame flex |
| J12 | Battery pack | 6-pin 2.5 mm power connector with lock (JST GH/XA-class, 3 A/pin) or Molex Nano-Fit for 10 A | Pack + SMBus + NTC |
| J13 | SoC debug UART | 4-pin 1.0 mm (unpopulated at PVT) | |
| J14 | EC SWD | Tag-Connect TC2030 footprint | No component |
| J15, J16 | Spare PCIe Gen2 ×1 test headers (pcie2x1l0, pcie2x1l2) |
0.5 mm 20-pin FPC footprint each, unpopulated | pcie2x1l0 was the v0.1 modem lane; the spare RK3588 USB 2.0 host (v0.1 modem AT channel) lands on a 4-pin test pad group |
| J17 | Fan header (reserved) | 3-pin 1.25 mm, unpopulated | For a future tunnel-fan variant |
| — | 2× MHF4 (Wi-Fi) | on the M.2 Key-E module, not the MB |
Renumbering note (v0.2): v0.1 refs J8 (M.2 Key-B), J11 (nano-SIM tray) and J12 (MFF2 eSIM) are deleted; J9–J19 shift down accordingly (v0.1 J9→J8, J10→J9, J13→J10, J14→J11, J15→J12, J16→J13, J17→J14, J18→J15, J19→J17).
9.2 Reader daughterboard
| Ref | Function | Part class | Notes |
|---|---|---|---|
| J1 | CFexpress Type B slot | Push-push, deep-insertion, metal cage, 10 k cycles | Molex/Amphenol CFexpress B receptacle family |
| J2 | CFexpress Type A slot | Push-push, 10 k cycles | |
| J3 | SD UHS-II slot | 17-pin push-push, deep-insertion, 10 k cycles | Hirose/Molex UHS-II family |
| J4 | microSD slot | Push-push, 10 k cycles, with card-detect | Molex 5033982-class |
| J5 | CFast 2.0 slot | 7+17 SATA-style CFast receptacle, 5 k cycles | Amphenol/3M CFast family |
| J6 | Mezzanine to MB | Samtec ADF6-40-01.5-x-x-2 (female, 80 pos.) | |
| J7 | LED bar | 5× RGB addressable LEDs on-board, or 4-pin FPC to a light-guide flex | Decide at industrial design |
9.3 Battery pack PCB
| Ref | Function | Part class |
|---|---|---|
| J1 | Pack output | Mates MB J12 |
| — | Cell tabs | Nickel strip welded to 21700 cells, soldered to pads |
10. Test and debug
- SoC UART on J13 through PVT; footprint remains, component removed, and the console is disabled in firmware and by OTP at PVT.
- EC SWD via Tag-Connect footprint; APPROTECT enabled at PVT.
- RK3588 JTAG is not brought out; debug is via UART and the vendor's USB maskrom mode on OTG0 (the spare USB3 port) — OTG0 is routed to a 4-pin test pad group for factory flashing, disabled by OTP at PVT.
- Boundary test points: 1 mm pads on all EC GPIOs, all power rails, I²C/SMBus, PERST#/CLKREQ# lines, eFuse outputs, and PD controller status. None on high-speed pairs.
- ICT: the main board is bed-of-nails testable before SoM and M.2 modules are installed (all test pads on L10, the front-facing side). After assembly into the enclosure there is no test access; the enclosure is sealed. Hence:
- FCT at the PCBA stage with SoM fitted: a fixture with card emulators (an NVMe SSD in a CFe B adapter, UHS-II SD, CFast card), loopback on Ethernet (5GbE), a USB host on Port A, a USB network-class tether emulator (e.g. a Linux gadget board presenting CDC-NCM) and a USB SSD on Port B with VBUS current-limit verification at 0.5 / 1.5 / 3 A (3 A only with a PD source present on Port A, D13), and current measurement on every rail. Test firmware exercises every PCIe endpoint and logs eye margin via the RK3588 and ASM2812 internal lane-margining registers where available.
- Base fixture does not exercise Port C (D7 decoupling): Port C is a blanked receptacle with the ASM2464PD, PD-C and mux depopulated; the Base test only confirms the empty footprints (no VBUS on J6, mux bypass present). Base is fully testable and shippable without any Port C hardware or firmware.
- Pro fixture adds: a USB4 host on Port C (native NVMe enumeration and UAS fallback through a USB 3.2 Gen2 host), the mode-switch sequence 20 times, the ASM2464PD firmware load, the Port C PD sink test with a PD source emulator (15 W and 65 W contracts; Port A priority and break-before-make on the TPS2121 mux with both ports powered; no charger-input glitch), and the read-only enforcement checks (NWPC set/clear on an NWPC-capable test card; bridge WP if exposed).
- The ODM typically owns the FCT/ICT fixtures and line NRE (D12); the two fixture definitions above are handed over as requirements in the ODM design-review package, with the Pro fixture allowed to lag Base.
- Final test after box build: over Port A (management network) and BLE only; runs the same self-test, plus shutter Hall, button, OLED, LEDs, and a 5-minute charge/discharge cycle.
11. DFM / DFA
- Panelization: MB 2-up, RB 4-up, with V-score and mouse-bites at the RB's connector edge avoided (tab routing only) to protect the slot alignment datum.
- Connector strain relief: every external connector's mechanical load is taken by the chassis, not the PCB. USB-C receptacles are mid-mount with shell tabs soldered and clamped by a machined chassis boss that surrounds the receptacle to within 0.1 mm; the RJ45 has a chassis shroud that engages the plug's latch and takes lateral loads. The PCB sees only the electrical connection.
- Sealing: IP67 USB-C receptacles seal to the chassis with an O-ring on the receptacle's front flange; the RJ45 relies on the hinged silicone door (IP54 only). Card slots seal via the shutter, not at the connector.
- Mid-mount receptacles require a board cutout; the cutout edges are plated and grounded to keep the L2 reference continuous under the SuperSpeed escape.
- Component height under the battery: L10 is limited to 2.0 mm component height in the region under the pack; the EC, PD controllers and passives comply. Bucks with 4 mm inductors are placed outside that region.
- M.2 standoffs are chassis-pressed inserts, not PCB-soldered, so the module screw load goes into the chassis; in magnesium the inserts are aluminum or zinc-nickel-plated (no brass or stainless in contact with Mg, D4).
- SoM retention: two M2 screws (Zn-Ni-plated steel or aluminum) into aluminum / Zn-Ni inserts in chassis bosses in addition to the B2B connectors, to survive the 26-drop sequence. Not applicable if PoC exit selects board-down (D12).
- Assembly order: RB is built and tested alone; MB built and ICT'd; SoM + M.2 modules fitted; FCT; MB screwed to chassis; RB slid onto its rail and mated; pack installed; front frame closed.
- Rework: shield cans with removable lids; ASM2464PD and ASM2812 on 0.5 mm-pitch BGA/QFN — X-ray sample at EVT.
12. High-speed simulation deliverables before EVT fabrication
| # | Deliverable | Tool class | Pass criterion |
|---|---|---|---|
| 1 | Stackup impedance and loss report from the fab (Megtron 6 hybrid), including measured Dk/Df coupons | fab + Polar | Zdiff within ±7 %, loss ≤ modelled +10 % |
| 2 | USB4 channel S-parameters: ASM2464PD pin → J6 receptacle mating plane, including via and AC-cap models | 3D EM (HFSS/CST or Simbeor) on extracted layout | IL ≤ 4 dB at 10 GHz, RL ≤ −10 dB to 10 GHz, ILD ≤ 0.5 dB; check against USB4 device-side eye mask with ASM2464PD IBIS-AMI if obtainable, else with generic USB4 TX/RX AMI |
| 3 | Gen4 mux path S-parameters: CFe B connector → RB → mezzanine → MB → PI3DBS16412 → ASM2464PD, with the mux vendor's S-parameter model cascaded | 3D EM + cascade | IL ≤ 8 dB at 8 GHz, RL ≤ −8 dB; PCIe Gen4 eye at ASM2464PD RX with CTLE/DFE presets |
| 4 | Gen3 path check for the two longest routes (SoM → switch → M.2 M-key; SoM → switch → mezzanine → GL9755) | 2.5D field solver | IL ≤ 8 dB at 4 GHz |
| 5 | REFCLK jitter budget: RK3588 REFCLK → clock mux → slot; ASM2464PD REFCLK → mux → slot | phase-noise cascade | ≤ 0.5 ps RMS post-filter (PCIe Gen4 CC filter) |
| 6 | Crosstalk on the mezzanine (Gen4 pairs adjacent to Gen3 pairs) | connector S-params | NEXT/FEXT ≤ −30 dB to 8 GHz |
| 7 | PDN: 5.0 V SYS rail impedance; 5.0 V PORT B rail 0→3 A attach step; 3.3 V slot rail CFe B inrush; 1.05 V cores | PDN solver + SPICE | ≤ 5 % droop; target impedance met to 100 MHz |
| 8 | Ethernet MDI skew and return loss | 2.5D | intra-pair skew ≤ 50 ps; pair-to-pair balance per IEEE 802.3bz |
| 9 | Mode-switch power sequence timing (SPICE of eFuse, active discharge, 100 µF card load) | SPICE | slot rail < 0.3 V within 150 ms of PWR_EN low |
| 10 | Port C PD mux transient (Pro): TPS2121-class priority mux hand-over — Port A attach while Port C is powering, Port C detach under 65 W load, both-ports-powered steady state — with the BQ25792 input model and mux break-before-make timing | SPICE (TI mux + charger models) | break-before-make: no overlap (zero reverse current into the released receptacle); charger input stays above BQ25792 VBUS UVLO through the gap (no charger-input glitch, no NVDC hiccup); VSYS droop ≤ 5 %; mux dissipation ≤ rating at 3.25 A / 20 V (verify) |
Items 2 and 3 are gating: EVT boards are not released to fab until both pass. Everything else can be run in parallel with fab and fixed at EVT-2 if needed; item 10 is only gating for the Pro population and may follow the Base build (D7).
13. Open items
- Sourcing of a sealed, USB4-rated USB-C receptacle for Port C (J6). If none, Port C uses an unsealed USB4 receptacle with a moulded silicone boot — a mechanical change (
08-mechanical.md). - ASM2812 and ASM2464PD reference schematics and firmware tools are under ASMedia NDA; ASMedia is primary (D12) through the owner's ASMedia-access team, engaged at PoC start. Fallback switch PEX8724 (larger package, +2 W) is retained as insurance until EVT schematic freeze. Fallback bridge: none with equivalent USB4 fallback behaviour; Port C is Pro-only and decoupled from Base, so it slips to a later Pro revision rather than de-scoping the product if the ASM2464PD is unavailable (D7). Also verify with the ASMedia team whether the ASM2464PD firmware tool exposes a read-only / write-protect configuration in UAS mode (D8).
- SoM vs board-down (D12), PoC exit: if board-down RK3588J is selected, §1.1, §2.1 (likely 12 layers), §7 and §9.1 J1/J2 change materially at EVT; this revision carries the SoM-carrier layout.
- TPS2121 rating at 20 V / 3.25 A (65 W) for the Port C / Port A priority mux (verify); alternates TPS2120 or an ideal-diode pair with EC-controlled priority.
- Confirm PI3DBS16412 S-parameter model availability from Diodes before committing the mux path budget in §3.2.
- Exact ADM6/ADF6 variant (stack height, ground-pattern option) to be fixed once
08-mechanical.mdsets the RB-to-MB spacing.