docs/04-component-selection.md
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# PoppyUp — Component Selection **Phase 1 deliverable #4.** Source of truth for the final picks is `00-architecture-decisions.md` (ADR, **Baseline v0.3 — owner review decisions D1–D13 applied**, change record ADR §15; the built-in 5G modem was removed in v0.2, ADR §14 and §(j) below). This document records the alternatives that were considered for each subsystem, the comparison data, and the reasoning. Pricing is budgetary at 1 k units, distributor/direct quotes, USD, mid-2026. Anything marked **(verify)** is a datasheet value I am quoting from memory and that must be confirmed against the current vendor document before schematic release. Related: `02-system-architecture.md` (topology), `03-datapath-bottlenecks.md` (why the speed numbers matter), `05-power-budget.md` (rails), `10-bom.md` (costed roll-up), `11-certification.md` (module certification leverage). --- ## Selection principles 1. **Proven and obtainable over exotic.** Every high-risk part (switch, USB4 bridge) must already ship inside a consumer or industrial product we can buy and tear down.2. **Mainline Linux driver, or a vendor driver with a credible upstream path.** The firmware phase must not inherit an out-of-tree kernel for a bridge chip.3. **Second source or footprint-compatible alternate** for anything with a single fab or NDA-gated documentation.4. **Industrial temperature grade** where the part sits near a heat source (SoM, switch, Ethernet PHY).5. **Modular where the market moves** (Wi-Fi, NVMe on M.2; card reader on a daughterboard), fixed where it does not (SoC, power). --- ## (a) SoC | Criterion | Rockchip RK3588 | NXP i.MX 95 | Qualcomm QCS6490 | Raspberry Pi CM5 (BCM2712) | Intel N100 (Alder Lake-N) ||---|---|---|---|---|---|| CPU | 4× A76 @ 2.4 GHz + 4× A55, 8 nm | 6× A55 @ 2.0 GHz + M7 + M33 | 4× A78 (Kryo 670 Gold) + 4× A55 | 4× A76 @ 2.4 GHz | 4× Gracemont E-cores @ 3.4 GHz || PCIe | 4× Gen3 lanes (×4 / ×2+×2 bifurcation) + 3× Gen2 ×1 combo lanes = 7 lanes | 2× Gen3 ×1 controllers (verify) | 1× Gen3 ×2 + 1× Gen3 ×1 (verify) | 1× Gen2 ×1 (Gen3 unofficial), shared with RP1 I/O | 9× Gen3 lanes, up to ×4 ports (verify) || USB device (gadget) | 2× USB 3.0 (5 Gbps) dual-role, dwc3, mature | 1× USB 3.0 dual-role | 1× USB 3.1 Gen1 dual-role (verify) | 1× USB 2.0 dual-role only (USB 3 is via RP1, host-only) | None practical (xDCI not exposed on N-series) || Native Ethernet | 2× 1 GbE RGMII | 2× 2.5 GbE (one TSN) | 1 GbE (via PHY) | 1 GbE (RP1) | none native; I226-V on PCIe || Crypto | ARMv8 CE (AES/SHA) on all 8 cores + Rockchip crypto v2 engine | ARMv8 CE + EdgeLock secure enclave | ARMv8 CE | ARMv8 CE | AES-NI, SHA-NI || Realistic TLS/upload CPU headroom | AES-128-GCM ≈ 1.5–2 GB/s per A76; SHA-256 ≈ 1 GB/s per A76; one A76 saturates 5GbE TLS with margin | A55 ≈ 0.6–0.8 GB/s AES-GCM per core; 5GbE TLS needs 2–3 cores; SFTP single-stream bound ≈ 250 MB/s | similar to RK3588, slightly better perf/W | equal to RK3588 per core, but no I/O to feed it | best single-thread; ≈ 3 GB/s AES per core || Mainline Linux | Good since 6.6–6.9: PCIe, USB3, GMAC, crypto, thermal, PM. Gaps: some display/VPU (irrelevant), PCIe ASPM quirks | Excellent (NXP upstream-first) | Good and improving (Qualcomm upstream push, RB3 Gen2), some blobs | Excellent | Excellent || Power (SoM-level, idle / heavy I/O) | 1.8 W / 5.5 W | 1.2 W / 3.5 W | 1.0 W / 4 W | 1.5 W / 5 W | 3.5 W / 12 W || Availability / longevity | High volume; Rockchip states 10-year for industrial RK3588J (verify); many SoM vendors | NXP 15-year longevity program; production ramp 2025 | Qualcomm 10+ yr program, via CSPs (Thundercomm, Lantronix) | Available; Raspberry Pi longevity to 2036 | Intel IoT longevity ≈ 10 yr; many COM Express/SMARC vendors || SoM cost @1k (8 GB / 64 GB) | $85–110 | $140–190 | $150–220 | $75 (8 GB) | $110–160 || Documentation access | Datasheet public; TRM public (partial); Rockchip SDK via SoM vendor | Full public docs | Under NDA/CSP | Public but thin (BCM2712 has no public TRM) | Full public docs || Kill criterion for us | — | Only 2 Gen3 lanes: CFe B capped at ~900 MB/s | Lane budget and docs gating | One PCIe lane for everything | No USB device mode; 2–3× power | **Pick:** Rockchip **RK3588** (RK3588J industrial bin). The *carrier form* — which SoM, or board-down — is **undecided (D12)** and is settled at PoC exit; see (b). **Why:** It is the only candidate in the price class with both a Gen3 ×4 root that bifurcates (dedicated ×2 for CFexpress B plus ×2 for the switch) *and* two dual-role USB 3 controllers with a mature dwc3 gadget stack. The A76 cores have hardware AES/SHA so TLS, per-part MD5/SHA-256 and xxHash for a 5GbE upload fit on one or two cores. The SoM ecosystem is the broadest of any ARM SoC outside of Raspberry Pi, and the community's PCIe experience (NVMe, modems, Wi-Fi 7 cards on ROCK 5B/Orange Pi 5 Plus) de-risks exactly the peripherals we are attaching. **Risks:** Rockchip mainline still lags vendor kernel for power management (suspend-to-RAM on some SoMs is fragile); dwc3 UAS gadget (`f_tcm`) is less battle-tested than `f_mass_storage` (mitigation: ship BOT mass storage first, UAS behind a flag); the 8 nm SoC needs a good heat path (see `06-thermal.md`); Rockchip documentation quality is mixed, and errata arrive through SoM vendors rather than a formal errata sheet. ## (b) System-on-Module | Criterion | Firefly Core-3588J | Forlinx FET3588-C | Board-down RK3588J (ODM reference design) | Turing Machines RK1 (dev kit) ||---|---|---|---|---|| SoC bin | RK3588J (−40…85 °C) | RK3588 / RK3588J option | RK3588J, sourced by the ODM | RK3588 (commercial) || PCIe exposed | 4× Gen3 + 3× Gen2 combo (verify pin-out) | 4× Gen3 + Gen2 combo (verify) | All 7 lanes directly at the BGA; bifurcation is ours to set | 1× Gen3 ×4 + 2× Gen2 ×1 (Jetson-compatible SODIMM-260) || USB3 OTG exposed | both | both | both | 1 OTG + 1 host (verify) || Connector | 3× 100-pin board-to-board (verify) | 4× 80-pin B2B | none — removes the connector stack from the 6.5 mm rear-face Z-budget | SODIMM-260 (Jetson pin-compatible) || Memory / storage options | 4–32 GB LPDDR4x, 32–256 GB eMMC | 4–16 GB, 32–128 GB | 8 GB LPDDR4x + 64 GB eMMC + RK806 PMIC placed on our main board (ODM sources) | 8–32 GB, 32–256 GB || Longevity statement | 10 yr (industrial line) | 10 yr | Rockchip RK3588J 10 yr (verify); no SoM-vendor dependency, but DDR/eMMC/PMIC longevity becomes ours | none formal || Price @1k (8/64) | ~$95 | ~$100 | SoC + DDR + eMMC + PMIC ≈ $60–70 (verify) plus a 12-layer main board and ~$120 k NRE; nets $25–35/unit lower at volume | ~$110 (retail-ish pricing) || Dev board / carrier reference | ITX-3588J, AIO-3588J | OK3588-C | The ODM's own RK3588 reference design — path only viable if it exists and has shipped | Turing Pi 2 | **Pick:** **UNDECIDED — PoC bake-off (D12), decided at PoC exit (month 2).** Three paths are evaluated side by side at PoC (`13-roadmap.md` §1):1. **Firefly Core-3588J** SoM (8 GB / 64 GB) — the v0.2 default; carried in `10-bom.md` for costing until the decision.2. **Forlinx FET3588-C** SoM — pin-incompatible with Firefly; carrier respin ~3 weeks.3. **Board-down RK3588J** on the main board, using the ODM's RK3588 reference design. **PoC comparison criteria (ADR §3.1):** `pcie3x4` ×2+×2 bifurcation and exposure of all 7 lanes; both USB3 OTG ports with dwc3 gadget (UAS/BOT to iOS/macOS); thermal interface (SoC top height, boss geometry, measured ΔT at 8 W); longevity and EOL terms in writing (≥ 5 years); price at 1 k / 10 k; second-source / pin-compatibility story; the ODM's ability to support the path. **Dev-kit:** Turing RK1 in a Turing Pi 2 or Jetson-style carrier for PoC bring-up only. **Board-down RK3588J (path 3).** *Pros:* no board-to-board connector stack (frees ~1.5–2 mm of the rear-face Z-budget and the SoM retention screws), the single-vendor SoM continuity risk disappears, lowest unit cost at volume ($25–35/unit below the SoM, `10-bom.md` cost-down levers), and the heat path is a direct SoC-lid-to-boss pad rather than SoM spreader + pad. *Cons:* LPDDR4x and PMIC layout and power-sequencing move onto our 10→12-layer main board (a major EVT layout delta, `09-pcb-architecture.md` §1), DDR/eMMC/PMIC sourcing and the RK boot firmware (SPL/TF-A/U-Boot, DDR training blobs) land on the ODM, and PoC cannot be done on the real board — the path is evaluated on the ODM's reference board. **Only viable if the ODM has a proven, shipped RK3588 reference design**; otherwise it is dropped at PoC exit. **Why Firefly was the v0.2 default:** Industrial bin, formal longevity, all seven PCIe lanes and both OTG ports on the connectors, and Firefly's carrier reference designs already show ×2+×2 bifurcation and M.2 module integration. **Risk:** the SODIMM-style modules (RK1) do not expose the second Gen3 ×2 controller, so PoC data on RK1 has to be replicated on the actual candidate carriers before EVT. ## (c) PCIe packet switch | Criterion | ASMedia ASM2812 | ASMedia ASM2824 | Broadcom PEX8724 | Diodes PI7C9X3G808GP ||---|---|---|---|---|| Lanes / ports | 4 up + up to 12 down (Gen3) | 8 up + up to 24 down (Gen3) | 24 lanes, 6 ports, Gen3 | 8 lanes, up to 8 ports, Gen3 || Fits our need (2 up + 9 down)? | Yes | Yes (oversized) | Yes | No (8 lanes total → 2 up + 6 down) || Typical power | ~1.8 W active, ~0.5 W ASPM (verify) | ~3 W | ~4–5 W | ~1.2 W || Package | 14×14 mm class BGA (verify) | 19×19 BGA | 19×19 BGA | 10×10 QFN/BGA || Docs | Datasheet under NDA via distributor; reference designs common | NDA | Public (Broadcom docs portal, registration) | Public || Hot-plug on downstream ports | Yes (used in NVMe enclosures) | Yes | Yes | Yes || In shipping products we can tear down | Quad-M.2 carrier cards, 2-bay TB enclosures | Quad/8× M.2 carriers | Server risers | Industrial boxes || Cost @1k | ~$12 | ~$22 | ~$35 | ~$14 | **Pick:** **ASM2812**, wired ×2 upstream — **ASMedia is primary (D12)**: the owner has a team with ASMedia parts and documentation access, which removes the distributor/NDA gate that made the switch a top risk in v0.2. **Fallback:** PEX8724 retained as insurance, re-confirmed at EVT schematic freeze (it costs +2.5 W and +$23 and needs a bigger heat path — a fallback, not a peer). **Why:** Lowest power in the class that has enough lanes, transparent (no firmware needed for basic switching, EEPROM optional), proven with Linux hot-plug in the same job (NVMe enclosures behind USB4 bridges). **Risk:** documentation remains NDA-gated; the ASMedia-access team and the ODM engaged in v0.3 (D12, ODM design-review package before EVT) cover it, and R2 in `12-risks-open-questions.md` is re-scored accordingly. ## (d) PCIe 2:1 mux (CFexpress B slot ↔ SoC / USB4 bridge) | Criterion | Diodes PI3DBS16412 | TI TMUXHS4412 (verify) | ASMedia ASM1480 ||---|---|---|---|| Rate | 16 GT/s (PCIe 4.0), 2 lanes (4 diff pairs) 2:1 | 16 Gbps class, 4 channels 2:1 (verify) | 8 GT/s (PCIe 3.0) || Insertion loss | ~1 dB @ 8 GHz (verify) | ~1 dB | ~1 dB @ 4 GHz || Package | 42-pin TQFN 3.5×9 mm class | 42 WQFN | 40 QFN || Power | <50 mW | <50 mW | <50 mW || Cost @1k | ~$2.80 | ~$3.20 | ~$1.50 | **Pick:** **PI3DBS16412** (plus a PI3PCIE2212-class 1-lane part or a clock-mux for the 100 MHz REFCLK). **Why:** Gen4-rated so the ASM2464PD-to-card link on the Pro SKU runs Gen4 ×2 (~3.5 GB/s) unencumbered; ASM1480 would cap the host path at Gen3. **Risk:** a passive mux eats ~1 dB of the Gen4 channel budget — keep slot-to-mux-to-bridge routing under ~60 mm on low-loss laminate (see `09-pcb-architecture.md`). ## (e) USB4 / host bridge for the CFexpress "FAST" path | Criterion | ASMedia ASM2464PD | Intel JHL8440 (Goshen Ridge) | SoC dwc3 gadget only ||---|---|---|---|| Upstream | USB4 40 Gbps / TB3 compatible | USB4 40 Gbps hub/dock | USB 3.0 5 Gbps || Downstream | PCIe Gen4 ×4 | PCIe Gen3 ×4 + USB3 hub ports + DP | — || Behaviour with USB 3.2 host (iPhone Pro, older Macs) | Falls back to **USB 3.2 Gen2 UAS NVMe bridge** — the NVMe card appears as a plain UAS disk (works with iPhone Files app) | Falls back to a USB 3.2 hub; PCIe tunnel unavailable → card invisible unless another device is behind the hub | Works everywhere at ≤ 400 MB/s || Realistic throughput to Mac/PC | ~3.0–3.2 GB/s | ~2.8 GB/s (Gen3 ×4) | ~380–420 MB/s || Firmware / tooling | ASMedia firmware via distributor; enclosure vendors ship it daily | Intel TB developer program, NVM tooling gated | none || Certification | USB-IF USB4 optional; no Thunderbolt trademark claimed | Same, plus Intel TB program if branded | none || Cost @1k | ~$14 + PD companion ~$2 | ~$22 | $0 || Power | ~2 W active, off when Port C idle | ~2.5 W | — | **Pick:** **ASM2464PD** on a dedicated Port C (Pro SKU only, depopulated on Base, decoupled from the Base launch — D7). Universal **SoC gadget** on Port A on all SKUs. Both host paths are **read-only by default (D8)**. **Why:** It is literally the silicon inside the current crop of USB4 CFexpress 4.0 readers and NVMe enclosures, so its behaviour with macOS/Windows/iPadOS is already characterised. Its USB 3.2 fallback presents the NVMe card as a UAS disk, which is exactly what an iPhone 15/16/17 Pro needs to hit ~900 MB/s in Files. Goshen Ridge would let us put the gadget behind the same connector, but the PCIe tunnel disappears on USB 3 hosts, the tooling is gated, and the dock-class power/cost is not justified for one slot. A single-connector design that muxes USB4 lanes between two upstream controllers was rejected: it needs a 20 GBd-class mux and coordination between two PD stacks — a schedule risk for a marginal UX gain. **Risks:** ASM2464PD firmware quality varies by revision (sleep/wake, some hosts fail to re-enumerate after suspend); we must lock a firmware version and regress it across host OS updates. Two data connectors need clear labelling. **Read-only enforcement (D8).** Source media must never be modified without explicit consent, and macOS writes `.Spotlight-V100`, `.fseventsd`, `.Trashes` and `._*` files to any writable volume. Port A is simple: the SoC gadget sets the SCSI write-protect bit on every UAS/BOT LUN. Port C has no gadget in the path, so enforcement is layered (ADR §4.2, `02-system-architecture.md`):1. **NVMe Namespace Write Protection** (NVMe 1.4 Set Features, Feature 0x84, state 1 "Write Protect"): the SoC, which owns the card until the mux flips, sets it before the flip; the host then sees a read-only namespace in both native USB4 and UAS-fallback modes. It works **only on cards whose controller reports NWPC support (Identify Controller byte 531)** — expected to be a minority of camera cards; the card library in `13-roadmap.md` records NWPC per card at PoC. State 2 ("until power cycle") is unusable because the mode switch power-cycles the slot.2. **ASM2464PD bridge write-protect**, UAS/BOT fallback mode only (iPhone and USB 3.2 hosts): the bridge's SCSI Mode Sense WP bit or a firmware read-only configuration, **if ASMedia's firmware tool exposes it — verify with the owner's ASMedia-access team at PoC**. Has no effect in native USB4/PCIe-tunnelled mode, where the host talks to the card's NVMe controller directly and no bridge logic is in the data path.3. **Fallback (native USB4 host + card without NWPC):** read-only cannot be enforced, so the device does not switch automatically; the OLED and app ask "Mac wants write access to CFe B — allow?" and the user consents per session; the session is logged and the job engine re-verifies the card (identity + directory/mtime scan) on return. Tracked as a risk in `12-risks-open-questions.md`. ## (f) Card controllers ### SD (full-size, UHS-II) | Criterion | Genesys GL9755 | Realtek RTS5260 | Realtek RTS5306E ||---|---|---|---|| Host interface | PCIe Gen3 ×1 (verify) | PCIe Gen2 ×1 | USB 3.2 Gen1 || SD support | UHS-II FD156/HD312, UHS-I | UHS-II, UHS-I | UHS-II || Linux | `sdhci-pci-gli` mainline (since 5.5) | `rtsx_pci` mainline | `rtsx_usb` mainline || Why not | — | Aging part, availability thinning | Not PCIe → not on the switch fabric; would need SoC USB host port || Cost @1k | ~$3.80 | ~$3.50 | ~$2.50 | **Pick:** **GL9755.** UHS-II is what V90 cards use; measured ~280–300 MB/s. **Upgrade path:** Genesys **GL9767** (SD Express PCIe pass-through + UHS-I) is roughly footprint-class compatible (verify) if SD Express ever gets camera traction. UHS-III has no cards; SD Express cards fall back to UHS-I in our slot. ### microSD | Criterion | Genesys GL9750 | Realtek RTS5227S | RK3588 native SDMMC ||---|---|---|---|| Host interface | PCIe Gen2/3 ×1 | PCIe Gen2 ×1 | SoC SDIO controller || Speed | UHS-I SDR104 (~95 MB/s) | UHS-I | UHS-I SDR104 || Linux | `sdhci-pci-gli` | `rtsx_pci` | `dw_mmc-rockchip` || Fabric | On ASM2812 → same enumeration path as every other slot | On ASM2812 | Not on PCIe; still exportable via gadget LUN, but a different code path and the SoM's SDMMC pins are often used for the SoM's own boot media || Cost @1k | ~$2.20 | ~$1.80 | $0 + connector | **Pick:** **GL9750.** Consistency of the block-device path and freedom from SoM pin-mux constraints beat saving $2. Tradeoff acknowledged: the SoC-native option would work in gadget mode too, but not via a future host-side switch path, and it drags the reader board into the SoM's boot pin-mux. ### CFast 2.0 (SATA III) | Criterion | ASMedia ASM1064 | ASMedia ASM1166 | RK3588 combo-PHY SATA ||---|---|---|---|| Host | PCIe Gen3 ×1 → 4× SATA 6 Gb/s | PCIe Gen3 ×2 → 6× SATA | Native SATA on combo PHY || Linux | AHCI, mainline | AHCI, mainline | AHCI, mainline || Fits | 1 lane, tiny | wasteful | Consumes one of the three Gen2 combo lanes (Wi-Fi + two spares since v0.2 freed the modem lane — so now viable, but SATA would then cross the mezzanine as a second signal class; ASM1064 keeps CFast on the same Gen3 ×1 scheme as the other reader-board controllers) || Cost @1k | ~$3.50 | ~$6 | $0 | **Pick:** **ASM1064** on the switch. CFast cards read ~500–550 MB/s; a Gen3 ×1 lane behind the switch supports that (the ADR's ≥380 MB/s floor assumes Gen2 fall-back if the lane is ever moved to a combo PHY). ### XQD**Not supported (D10).** XQD is physically compatible with the CFe B connector but uses a proprietary non-NVMe PCIe protocol with no Linux driver; no licensing and no USB-reader workaround are pursued. The only related behaviour is firmware detecting a non-NVMe PCIe device in the CFe B slot and showing "XQD not supported". ## (g) USB 3.2 host controller (Port B "SSD / TETHER") | Criterion | ASMedia ASM3142 | ASMedia ASM3242 | RK3588 OTG0 ||---|---|---|---|| Upstream | PCIe Gen3 ×2 | PCIe Gen3 ×4 | — || Ports | 2× USB 3.2 Gen2 (10 Gbps) | 1× Gen2×2 (20 Gbps) | 1× 5 Gbps || Realistic SSD ingest | ~900 MB/s | ~1.7 GB/s but almost no SSDs/hosts use Gen2×2 | ~400 MB/s || Linux | xHCI mainline | xHCI mainline | dwc3 || Cost @1k | ~$4.50 | ~$7 | $0 | **Pick:** **ASM3142** (one of two ports used; second to a test header). Samsung T7/T9 and Blackmagic-class SSDs are Gen2 devices; halving ingest speed to save $4.50 is a poor trade for a "future-proof" product. Since ADR v0.2 Port B is also the **tethered-uplink port** (ADR §4.3): a USB-tethered iPhone (`ipheth`), Android phone (`cdc_ncm` / `rndis_host`) or USB LTE/5G adapter (`cdc_mbim` / `qmi_wwan`) enumerates on the same xHCI. That needs no extra silicon — only a dedicated 5 V/3 A Port B buck (TPS62933 class) behind the Port B eFuse, with the 0.5 / 1.5 / 3 A limit set by the EC, so the phone is charged while tethered without coupling its charge-current steps into the SoM's 5 V rail (`05-power-budget.md` §3.3). The RK3588 OTG0 alternative would serve tethering equally well (phones tether at USB 2.0-class rates), but not SSD ingest. ## (h) Ethernet | Criterion | Realtek RTL8126 | Realtek RTL8125BG | Intel I226-V | Marvell AQC113C ||---|---|---|---|---|| Rate | 5G/2.5G/1G/100M | 2.5G/1G/100M | 2.5G/1G/100M | 10G/5G/2.5G/1G || PCIe | Gen3 ×1 | Gen2 ×1 | Gen3 ×1 | Gen4 ×1 / Gen3 ×2 || Power at top link | ~1.9 W | ~1.2 W | ~1.3 W | ~4–5 W (10GBASE-T PHY) || Driver | `r8169` mainline (6.9+) | `r8169` | `igc` | `atlantic` || Cable reality | 5G over Cat5e/6 short runs | any | any | Cat6a for 10G at length || Payload | ~590 MB/s | ~295 MB/s | ~295 MB/s | ~1180 MB/s || Cost @1k (MAC/PHY) | ~$5 | ~$3 | ~$6 | ~$18 || Magnetics | Integrated-magnetics RJ45 (5G-rated, e.g. Bel/Pulse/Würth) ~$3.50 | standard | standard | 10G-rated magjack ~$6 | **Pick:** **RTL8126 (5GBASE-T)**, 5G-rated integrated-magnetics RJ45 — **final (D6)**. **Why:** 10GBASE-T costs 3–4 W continuous in a sealed 10 W-class enclosure and ~$20 of BOM, for a link speed virtually no venue uplink can use; 5GbE already exceeds every card except CFexpress. No 10GbE footprint option or watch item is carried. ## (i) Wi-Fi / Bluetooth module (M.2 Key-E 2230) | Criterion | MediaTek MT7925 | Qualcomm QCNCM865 (WCN7850) | Intel BE200 | MediaTek MT7922 (Wi-Fi 6E) ||---|---|---|---|---|| Standard / streams | Wi-Fi 7 2×2, 160 MHz, 6 GHz, basic MLO | Wi-Fi 7 2×2, 320 MHz, MLO | Wi-Fi 7 2×2, 320 MHz, MLO | Wi-Fi 6E 2×2, 160 MHz || Peak PHY | 2.9 Gbps | 5.8 Gbps | 5.8 Gbps | 2.4 Gbps || Linux driver | `mt7925e` mainline (6.7+), FW in linux-firmware | `ath12k` mainline (6.7+) | `iwlwifi` mainline | `mt7921e` mature || AP + STA concurrency | Supported (mt76 family, 2 vifs, same-channel) | Supported in ath12k (maturing) | AP mode limited (no 6 GHz AP, regulatory-locked); effectively STA-only | Supported || Officially supported off-Intel platforms | Yes | Yes | No (works on many, unsupported) | Yes || Power (TX) | ~1.8 W | ~2.3 W | ~2.2 W | ~1.6 W || Module vendors | AzureWave AW-XB591NF, Fn-Link 6252M-PUB | Foxconn, AzureWave (limited) | Intel | AzureWave AW-XB468NF || Cost @1k | ~$11 | ~$16 | ~$13 | ~$8 | **Pick:** **MT7925** module (AzureWave AW-XB591NF or Fn-Link equivalent). **Why:** mainline driver with working AP+STA, lowest power, vendor-agnostic. 320 MHz is not worth the power: our upload is bottlenecked by the venue WAN, not the Wi-Fi PHY. **Alternate:** QCNCM865 if a 320 MHz spec bullet matters to marketing. BT lines are wired to a SoC USB 2.0 port but BLE duties live on the EC. ## (j) Cellular uplink — no built-in modem (ADR v0.2, confirmed final in v0.3 — D1) ADR v0.1 selected a Quectel RM520N-GL (Snapdragon X62, M.2 Key-B 3052, PCIe Gen3 ×1 / USB 3.1, mainline MHI) with RM551E-GL as an upgrade path, an RG255C RedCap "lite" option, a nano-SIM tray and an MFF2 eUICC. **ADR v0.2 removes the built-in modem entirely.** The full reasoning is ADR §14; the comparison that drove it: | Criterion | Built-in RM520N-GL (v0.1) | Built-in RG255C RedCap (lite option) | **Phone hotspot (Wi-Fi STA) / USB-tethered phone on Port B** | USB LTE/5G adapter on Port B (accessory) ||---|---|---|---|---|| Real-world uplink | 2.5–10 MB/s typical, 12–25 MB/s good C-band | 4–10 MB/s | same cell, same uplink as the built-in module (the phone *is* an X70/X75-class modem with a better antenna volume than ours) | same class as RM520N || BOM @1k | ~$146 incl. rail, SIM, eSIM, 4 antennas | ~$75 | $0 (+ ~$1.20 dedicated 5 V/3 A Port B buck) | $0 (retail $60–150, optional bundle) || Certification | PTCRB, GCF, GSMA TAC, AT&T, Verizon ODI, cellular SAR, EN 301 908: ~$100–150 k, long pole after DVT | same set, separate run | none — the phone carries it | none — the adapter maker carries it || Power | 0.4 W idle, 4.5–6 W TX, 12 W ms bursts, dedicated 5 A rail | ~1.5 W avg | 1.0 W Wi-Fi TX at 10 MB/s, or 0.8 W xHCI + optional 2.5–15 W phone charging | 2–4 W from Port B VBUS || Thermal | hottest sustained source in a sealed enclosure | moderate | the heat is in the phone | in the adapter || Mechanical | tallest rear-face part (6.5 mm), 4 end-cap antennas with RF windows, SIM penetration | 3042, same antenna set | nothing | nothing || Linux | `mhi_pci_generic` + `mhi_wwan_mbim`, ModemManager, eSIM LPA | USB `qmi_wwan` | `ipheth` (iOS), `cdc_ncm` / `rndis_host` (Android) — all mainline | `cdc_mbim` / `qmi_wwan`, or NCM/RNDIS for hotspot-class adapters — mainline || Failure modes | carrier firmware lock, 12–20 wk lead time, hung PCIe modem needing EC reset | same | iOS trust prompt on first attach, hotspot idle timeout, USB 2.0-class tether link (~30–40 MB/s, still 3–10× the cellular uplink), phone thermal throttling | adapter quality varies; keep a tested list | **Pick:** **no built-in modem.** Cellular reach = phone hotspot over Wi-Fi STA, USB-tethered phone on Port B, or a USB LTE/5G adapter on Port B (ADR §5). Firmware treats all three as metered links with per-link caps and warnings. **Why:** No module in the v0.1 table changed the fundamental fact that cellular uplink is 150–650× slower than the card (`03-datapath-bottlenecks.md`), and the user already carries a better-antenna'd 5G modem in their pocket. The built-in module bought no uplink and cost ~19–24 % of the BOM, the largest one-time certification line, the schedule's critical path, the hottest sustained heat source, the tallest rear-face part and one sealed penetration. **Adapter recommendation list (to be validated at PoC, `13-roadmap.md`):** iPhone 15/16/17 (USB-C, Personal Hotspot over USB), Pixel / Galaxy (USB tethering), and at least one retail USB adapter in each of the two Linux classes — an MBIM/QMI dongle (Quectel/Fibocom-module based) and a hotspot-class device that presents NCM/RNDIS (Netgear Nighthawk M-series or TP-Link/ZTE MF-series in USB tethering mode). ## (k) Antennas | Option | Band coverage | Form | Efficiency in our window | Cost @1k | Notes ||---|---|---|---|---|---|| Wi-Fi: Taoglas FXP840-class dual/tri-band flex (verify) | 2.4/5/6 GHz | 40×10 flex, MHF4 pigtail | good behind 1.8 mm PC+GF | ~$2 | 2 pcs, front-frame upper band, 118 mm apart || Wi-Fi: Molex / Antenova tri-band flex | 2.4/5/6 GHz | similar | similar | ~$2 | second source || Wi-Fi: custom LDS on PC frame | tuned | Laser-direct-structured on the PC+GF frame | Best, repeatable | ~$1.20/element + $15 k NRE | Optional PVT path — with only two elements the NRE pays back slowly; decide at DVT || BLE: chip antenna (Johanson 2450AT18 class) on EC | 2.4 GHz | SMD, 6 × 12 mm keep-out | fine behind PC window | ~$0.30 | | **Pick:** 2× Wi-Fi tri-band flex + 1× BLE chip antenna (3 antennas, 2 MHF4 cables). LDS on the PC frame is an optional PVT cost-down, not a plan of record. The v0.1 wideband cellular flex options (Taoglas FXUB66 / Antenova / Ignion) are deleted with the modem. Detail in `07-rf-antenna.md`. ## (l) Embedded controller | Criterion | Nordic nRF5340 | STM32U575 + Wi-Fi-module BT | Espressif ESP32-C6 ||---|---|---|---|| BLE | 5.4 LE integrated, own core | none — BLE only while SoC + Wi-Fi module awake | BLE 5.3 || Always-on power | ~50 mW with OLED, ~1 mA advertising | ~30 mW | ~80 mW || Secure boot / crypto | TrustZone-M, CryptoCell-312, MCUboot | TrustZone-M, SAU | Secure boot v2, flash encryption || Provisioning while SoC off | Yes | No | Yes || Toolchain | Zephyr (nRF Connect SDK) | Zephyr / STM32Cube | ESP-IDF || Supply / longevity | Nordic long-life | ST 10-yr | Espressif; less common in regulated gear || Cost @1k | ~$6.50 | ~$5 + $0 | ~$2.50 | **Pick:** **nRF5340.** BLE provisioning and status while the SoC sleeps is a core UX requirement (the device sits in a kit bag between jobs for weeks of standby); ESP32-C6 is cheaper but its 2.4 GHz coexistence, security story and vendor comfort in enterprise/regulated purchasing are weaker. ## (m) Security element | Criterion | Infineon OPTIGA TPM SLB9672 | NXP EdgeLock SE050 | Microchip ATECC608B | OP-TEE only (RK3588 HUK) ||---|---|---|---|---|| Standard | TPM 2.0, SPI, CC EAL4+ | JavaCard SE, I²C, CC EAL6+ | Crypto authentication IC, I²C | Software TEE on SoC || Linux stack | `tpm_tis_spi`, tpm2-tools, systemd-cryptenroll, measured boot | Plug & Trust middleware, PKCS#11 | cryptoauthlib | OP-TEE client || Sealing to boot state | Native (PCRs) | via app logic | limited | via OP-TEE + RPMB || Suits our blobs (OAuth tokens, S3 keys) | Yes — seal LUKS2 key, store identity key | Yes | Key storage only (no bulk) | Yes but SoC-bound and Rockchip-blob dependent || Cost @1k | ~$2.40 | ~$3.20 | ~$0.90 | $0 | **Pick:** **SLB9672** for boot-state-sealed disk encryption and device identity, with OP-TEE as a second layer. **Alternate:** SE050 if a customer demands EAL6+ or factory-injected credentials. ## (n) Power components | Function | Pick | Alternates | Reasoning ||---|---|---|---|| Charger | **TI BQ25792** (buck-boost NVDC, 1–4S, 5 A, I²C, PD-aware via TPS25750) | BQ25798 (adds MPPT — irrelevant), MPS MP2760 (2–4S buck-boost, cheaper, less Linux/EC tooling), Renesas ISL9241 (laptop NVDC, needs 2 inductors) | Single-inductor buck-boost handles 5–20 V PD input into a 2S pack, seamless system-power path on unplug, TI reference with TPS25750 || PD controller (Port A) | **TI TPS25750** | TPS65988 (dual-port, more flexible, $6), Infineon CCG7D (automotive-grade, firmware SDK heavier) | Preconfigured via web tool, direct I²C link to BQ2579x, sink + optional source role || PD/CC (Port B source) | TPS25750 (Port B, source 5 V/3 A) | TPS65988 single part for A+B | keep each port independent for failure isolation. Port B buck unchanged (TPS62933 class, (g)); the D13 rule "3 A only while external PD power is present, 1.5 A default on battery" is EC policy — no part change || PD sink controller (Port C, **Pro only**, D7) | **TI TPS25750** (third instance, sink role, I²C to EC) | TPS65988 (dual-port, would merge A+C) | Lets a Mac (typically 15 W; up to its advertised contract) power the device during long reader sessions. Depopulated on Base together with the ASM2464PD; the ASM2464PD's own companion PD remains per the ASMedia reference design for the data role || VBUS priority power mux (Port C ↔ Port A into the charger input, **Pro only**, D7) | **TI TPS2121** priority power mux: Port A priority, break-before-make, 5–20 V, ≤ 3.25 A (verify rating at 20 V / 65 W; if short, two TPS2121 in parallel or an ideal-diode pair) | TI TPS2120 (same family, lower current); onsemi / Diodes ideal-diode ORing pair with EC-controlled priority | ORs Port C VBUS with Port A VBUS at the BQ25792 input so both ports are charging inputs without back-powering the other receptacle. Base: mux depopulated, 0 Ω bypass from Port A || Fuel gauge / protector | **TI BQ40Z50-R2** (1–4S, Impedance Track, protection, SHA-1 auth) | BQ4050 (no IT accuracy), Maxim/ADI MAX17320 (2–4S, ModelGauge m5, compact) | Runtime/SOH estimates exposed to the app; industry-standard SBS data || Secondary protector | BQ294xx family | — | independent overvoltage || Cells | **Samsung INR21700-50E** (4.9 Ah, 9.8 A) | LG M50LT (5.0 Ah), Molicel P45B (4.5 Ah, 45 A — overkill), Li-Po pouch | Energy density at moderate current; UN 38.3-tested cells from three vendors; pouch rejected for drop/swelling robustness and custom UN 38.3 pack burden || Bucks | TI TPS62xxx / TPS56xxx class; Vicor/Monolithic alternates | — | see `05-power-budget.md` || eFuses (slots, USB VBUS) | TI TPS2596 / TPS25947 class | onsemi NCP38x | programmable current limit per slot | ## (o) Display | Criterion | 2.42" mono OLED (SSD1309, 128×64) | 2.13" e-paper (SSD1680, 250×122) | Sharp memory LCD LS027B7DH01 (2.7", 400×240) ||---|---|---|---|| Operating temp | −40…+70 °C | 0…+50 °C (verify; slow/ghosting below 5 °C) | −20…+70 °C (verify) || Sunlight | Marginal (high-contrast mono helps) | Excellent | Excellent (reflective) || Dark set / dim stage | Excellent (emissive) | Needs external light | Needs frontlight (not standard) || Refresh | instant | 300 ms partial, ~2 s full | 20 Hz || Power | 30–80 mW active, 0 asleep | ~0 static, mJ per update | 50–100 µW || Static image when device off | no (unless kept on) | yes | yes while powered || Drop robustness | small glass, easy to recess | larger glass, fragile | glass || Burn-in | yes — mitigated by auto-off | no | no || Cost @1k | ~$5 | ~$7 | ~$14 | **Pick:** **2.42" OLED**, driven by the EC, auto-off after 30 s with LED bar remaining. Film sets are often dim and winter exteriors are common; the e-paper 0 °C floor and slow refresh, and the memory LCD's dark-set problem, outweigh their sunlight advantage. Confirmed by the owner (D13, ADR §13.6). ## (p) Card connectors | Slot | Candidates | Pick | Notes ||---|---|---|---|| CFexpress Type B | Molex 2153230001 class push-push (verify), Amphenol CFexpress B push-push, Hirose (verify) | Molex, deep-insertion push-push, 10 k cycles | Must leave ≥ 1 mm of card below shutter plane; metal cage with thermal pad interface || CFexpress Type A | Molex / Amphenol CFe-A push-push (verify) | Molex | 10 k cycles || SD UHS-II | Molex 47219-class UHS-II push-push (verify), Hirose DM3 series | Molex | 17-pin UHS-II, 10 k cycles || microSD | Molex 5033982 class push-push | Molex | 10 k cycles || CFast 2.0 | Amphenol / 3M CFast (SATA 7+17) receptacle with ejector | Amphenol | 5 k cycles — lowest life of the set | ## (q) External connectors | Function | Candidates | Pick | Notes ||---|---|---|---|| USB-C ×3 | Amphenol IP67 mid-mount USB-C, JAE DX07 waterproof series, GCT USB4135 IP67 | Amphenol IP67 mid-mount, 24-pin (full USB4/PD) | Sealed at the receptacle flange with an O-ring; shell tabs anchored to the magnesium chassis for strain relief (boss coated; Zn-Ni or Al hardware, see (s)). Same part on all three ports and both SKUs: on Pro the Port C receptacle also carries the PD sink (D7) — no part change || RJ45 | Integrated-magnetics 5GBASE-T-rated magjack (Bel 0826-1X1T class, verify) vs discrete magnetics | Integrated magjack | Hinged silicone door for IP54; shield bonded to chassis | ## (r) Mezzanine (main ↔ reader daughterboard) | Criterion | Samtec ADM6/ADF6 | Hirose FX23 | Molex SlimStack 0.35 mm ||---|---|---|---|| Pitch / stack | 0.635 mm, 5–10 mm stack | 0.5 mm, 3–5 mm | 0.35 mm, 1.5–4 mm || Rated | 56 Gbps PAM4 (Gen4/5 ready) | Gen3/Gen4 (verify) | ~8 Gbps || Pins | 40–200 | 40–140 | 20–100 || Ruggedness | robust, guided | good | fragile under shock || Cost (pair @1k) | ~$9 | ~$6 | ~$3 | **Pick:** **Samtec ADM6/ADF6, 80-pin** (Gen4-capable for a future switch-side upgrade; shock-tolerant). Hirose FX23 as cost-down if DVT shows stack height allows. ## (s) Chassis material and finish (D4) The chassis-heatsink forms the rear and bottom skins and is the spreader for the SoM, switch and Ethernet PHY (`06-thermal.md`, `08-mechanical.md` §4). The owner selected **magnesium** in v0.3; aluminum (CNC 6061 prototypes, ADC12 die-cast production) is no longer planned. All material data **(verify)** against supplier datasheets. | Option | Use | k (W/m·K) | cp (J/g·K) | ρ (g/cm³) | Unit cost, incl. coating | Lead time | Thermal fidelity to production ||---|---|---|---|---|---|---|---|| **AZ91D hot-chamber die-cast** + boss machining | **Production (PVT/MP)** | ~72 | ~1.02 | 1.81 | ~$21 @10k | Tool ~14–18 wk; ~$62 k (Mg tool ≈ +12 % vs Al) | Reference || Machined AZ31B (plate/billet) | EVT/DVT thermal-validation units | ~96 (~30 % better than AZ91D) | ~1.0 | 1.77 | ~$58 @1k-class quantities | 3–4 wk, no tooling | Must be corrected −30 % on k before the EVT-exit fan gate is called || Thixomolded (or T0 die-cast) AZ91D | DVT alternative to machined AZ31B | ~72 | ~1.02 | 1.81 | ~$58 @1k incl. soft tool amortisation | Soft tool ~6–8 wk, ~$35 k (carried in the DVT budget, `13-roadmap.md` §8) | Same alloy as production — no correction needed || *Aluminum 6061 CNC / ADC12 die-cast (v0.2)* | *no longer planned* | *~167 / ~96* | *~0.90* | *2.70* | *$46 / $15* | *—* | *~935 g device vs ~828 g with Mg* | **Pick:** **AZ91D die-cast for production; machined AZ31B for EVT, with thixomolded AZ91D preferred for DVT** if the soft-tool lead time fits, so the fan gate (D5) is called on the production alloy. Walls 1.6 mm, draft ≥ 1°, bosses ≥ 2.5 mm wall with faces machined to 0.10 mm flatness, inserts for all threads (DFM list in `08-mechanical.md` §4). **Coating.** Pick: **chromate-free conversion coat over the whole casting (Gardobond X 4707 / Alodine 5200 class, ~1 µm) + light matte grey powder coat or e-coat 40–60 µm on all external surfaces** (ε ≈ 0.9 for radiation, light colour for solar load). **Masked bare-conversion pads** at the SoM / ASM2812 / RTL8126 gap-pad bosses and the EMI-gasket lands — a 60 µm organic coat under an 8 W boss would add ~5 K (verify). Alternate: plasma electrolytic oxidation (Keronite / Tagnite class, 15–25 µm ceramic) under the same top-coat if a salt-fog / marine claim is added later; rejected as baseline on cost and because the conversion + organic system is what the volume Mg laptop-chassis supply chain runs. POM shutter tracks are separate mouldings and need no coating. **Fasteners and inserts (galvanic).** Magnesium is anodic to everything else in the assembly, so: zinc-nickel-plated steel or 5056/6061 aluminum screws with aluminum washers in coated pockets; **no stainless helicoils** — aluminum or zinc-nickel-coated press-in / threaded inserts; stainless detent balls and springs sit in POM housings; the hard-anodized 6061 aluminum shutter slats never touch the chassis (POM tracks, silicone seals); conductive EMI gasket only on the masked conversion-coated lands. Verify contact resistance and 500 h neutral salt fog on coupons at EVT. --- ## Final pick list | Subsystem | Part | Qty | Alternate / second source ||---|---|---|---|| SoC / SoM | RK3588J; carrier **undecided — 3 candidates, PoC exit (D12)**: Firefly Core-3588J (costing default), Forlinx FET3588-C, board-down RK3588J on the ODM reference | 1 | the other two candidates || PCIe switch | ASMedia ASM2812 | 1 | Broadcom PEX8724 || CFe B PCIe mux | Diodes PI3DBS16412 + REFCLK mux | 1+1 | TI TMUXHS4412 (verify) || USB4 bridge (Pro) | ASMedia ASM2464PD + PD companion | 1 | — (depopulate on Base) || SD UHS-II controller | Genesys GL9755 | 1 | Realtek RTS5260 || microSD controller | Genesys GL9750 | 1 | Realtek RTS5227S || CFast controller | ASMedia ASM1064 | 1 | ASM1166 || USB host controller | ASMedia ASM3142 | 1 | ASM3242 || Ethernet | Realtek RTL8126 + 5GBASE-T magjack (final, D6) | 1 | RTL8125BG (2.5GbE, spec regression) || Wi-Fi 7 module | AzureWave AW-XB591NF (MT7925) | 1 | Fn-Link 6252M-PUB; QCNCM865 || Cellular modem | — none (ADR v0.2); phone tether / USB adapter on Port B | 0 | — || Port B 5 V/3 A tether buck | TI TPS62933 class, EC-programmable 0.5/1.5/3 A limit via the Port B eFuse | 1 | MPS MP2315 / TI TPS563300 || Wi-Fi antennas | Taoglas FXP840-class tri-band flex | 2 | Molex / Antenova || BLE antenna | Johanson 2450AT18-class chip antenna on EC | 1 | Pulse / Yageo || EC | Nordic nRF5340 | 1 | STM32U575 (loses standby BLE) || TPM | Infineon SLB9672 | 1 | NXP SE050 || Charger | TI BQ25792 | 1 | MPS MP2760 || PD controllers (Port A sink/source, Port B source) | TI TPS25750 | 2 | TPS65988 || Port C PD sink controller (Pro only, D7) | TI TPS25750 | 1 | TPS65988 (merging A+C) || Port C / Port A VBUS priority mux (Pro only, D7) | TI TPS2121, Port A priority, break-before-make, 5–20 V ≤ 3.25 A (verify at 65 W) | 1 | TI TPS2120; onsemi / Diodes ideal-diode pair || Fuel gauge / protector | TI BQ40Z50-R2 + BQ294xx | 1+1 | ADI MAX17320 || Cells | Samsung INR21700-50E | 4 | LG M50LT, Molicel P45B || Display | 2.42" SSD1309 OLED (confirmed, D13) | 1 | — || Card connectors | Molex CFe B, CFe A, SD UHS-II, microSD; Amphenol CFast | 5 | Amphenol / Hirose || USB-C receptacles | Amphenol IP67 mid-mount | 3 | JAE DX07 || Mezzanine | Samtec ADM6/ADF6 80-pin | 1 pair | Hirose FX23 || NVMe (Pro) | 1 TB M.2 2280 Gen3/Gen4 ×2-capable (e.g. Kioxia/WD industrial class) | 1 | any || Chassis material / finish (D4) | AZ91D hot-chamber die-cast magnesium, chromate-free conversion coat + matte grey powder/e-coat 40–60 µm, masked bare bosses; EVT/DVT units machined AZ31B or thixomolded AZ91D | 1 | PEO (Keronite/Tagnite) under the same top-coat for a salt-fog claim |